Datasheet AD7811, AD7812 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | 10-Bit, 8-Channel, 350 kSPS, Serial A/D Converter |
| Pages / Page | 24 / 3 — AD7811/AD7812. Parameter. Y Version. Unit. Test Conditions/Comments. … |
| Revision | C |
| File Format / Size | PDF / 336 Kb |
| Document Language | English |
AD7811/AD7812. Parameter. Y Version. Unit. Test Conditions/Comments. TIMING CHARACTERISTICS1, 2
Model Line for this Datasheet
Text Version of Document
link to page 12 link to page 12 link to page 3 link to page 3 link to page 4 link to page 4 link to page 3 link to page 15 link to page 15 link to page 16 link to page 3 link to page 3 link to page 3 link to page 3 link to page 3
AD7811/AD7812 Parameter Y Version Unit Test Conditions/Comments
POWER SUPPLY VDD 2.7 V min For Specified Performance 5.5 V max IDD Digital Inputs = 0 V or VDD Normal Operation 3.5 mA max Power-Down Full Power-Down 1 µA max Partial Power-Down (Internal Ref) 350 µA max See Power-Up Times Section Power Dissipation VDD = 3 V Normal Operation 10.5 mW max Auto Full Power-Down See Power vs. Throughput Section Throughput 1 kSPS 31.5 µW max Throughput 10 kSPS 315 µW max Throughput 100 kSPS 3.15 mW max Partial Power-Down (Internal Ref) 1.05 mW max Full Power-Down 3 µW max NOTES 1See Terminology. 2Sample tested during initial release and after any redesign or process change that may affect this parameter. Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2 (VDD = 2.7 V to 5.5 V, VREF = VDD [EXT] unless otherwise noted) Parameter Y Version Unit Conditions/Comments
t 1.5 µs (max) Power-Up Time of AD7811/AD7812 after Rising Edge of CONVST POWER-UP t 2.3 µs (max) Conversion Time 1 t 20 ns (min) CONVST Pulsewidth 2 t 25 ns (min) SCLK High Pulsewidth 3 t 25 ns (min) SCLK Low Pulsewidth 4 t 3 5 ns (min) RFS Rising Edge to SCLK Rising Edge Setup Time 5 t 3 5 ns (min) TFS Falling Edge to SCLK Falling Edge Setup Time 6 t 3 10 ns (max) SCLK Rising Edge to Data Out Valid 7 t 10 ns (min) DIN Data Valid to SCLK Falling Edge Setup Time 8 t 5 ns (min) DIN Data Valid after SCLK Falling Edge Hold Time 9 t 3, 4 20 ns (max) SCLK Rising Edge to D 10 OUT High Impedance t 100 ns (min) DOUT High Impedance to CONVST Falling Edge 11 NOTES 1Sample tested to ensure compliance. 2See Figures 16, 17 and 18. 3These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V DD = 5 V ± 10% and 0.4 V or 2 V for VDD = 3 V ± 10%. 4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 11, quoted in the Timing Characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances. Specifications subject to change without notice.
200
A IOL TO OUTPUT 2.1V PIN CL 50pF I 200
A OH
Figure 1. Load Circuit for Digital Output Timing Specifications REV. C –3– Document Outline Features General Description Product Highlights Functional Block Diagram Specifications Timing Characteristics Absolute Maximum Ratings ESD Caution Pin Configurations Pin Function Descriptions Terminology Signal to (Noise + Distortion) Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion Channel-to-Channel Isolation Relative Accuracy Differential Nonlinearity Offset Error Offset Error Match Gain Error Gain Error Match Track/Hold Acquisition Time Control Register (AD7811) Control Register (AD7812) Circuit Description Converter Operation Typical Connection Diagram Analog Input DC Acquisition Time AC Acquisition Time On-Chip Reference ADC Transfer Function Power-Down Options Power-On-Reset Power-Up Times Mode 2 Full Power-Down (PD1 = 1, PD0 = 0) Mode 2 Partial Power-Down (PD1 = 0, PD0 = 1) Power vs. Throughput Operating Modes Mode 1 Operation (High Speed Sampling) Mode 2 Operation (Automatic Power-Down) Serial Interface Simplifying the Serial Interface Microprocessor Interfacing AD7811/AD7812 to PIC16C6x/7x AD7811/AD7812 to MC68HC11 AD7811/AD7812 to 8051
AD7811/AD7812 Parameter Y Version Unit Test Conditions/Comments
POWER SUPPLY VDD 2.7 V min For Specified Performance 5.5 V max IDD Digital Inputs = 0 V or VDD Normal Operation 3.5 mA max Power-Down Full Power-Down 1 µA max Partial Power-Down (Internal Ref) 350 µA max See Power-Up Times Section Power Dissipation VDD = 3 V Normal Operation 10.5 mW max Auto Full Power-Down See Power vs. Throughput Section Throughput 1 kSPS 31.5 µW max Throughput 10 kSPS 315 µW max Throughput 100 kSPS 3.15 mW max Partial Power-Down (Internal Ref) 1.05 mW max Full Power-Down 3 µW max NOTES 1See Terminology. 2Sample tested during initial release and after any redesign or process change that may affect this parameter. Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2 (VDD = 2.7 V to 5.5 V, VREF = VDD [EXT] unless otherwise noted) Parameter Y Version Unit Conditions/Comments
t 1.5 µs (max) Power-Up Time of AD7811/AD7812 after Rising Edge of CONVST POWER-UP t 2.3 µs (max) Conversion Time 1 t 20 ns (min) CONVST Pulsewidth 2 t 25 ns (min) SCLK High Pulsewidth 3 t 25 ns (min) SCLK Low Pulsewidth 4 t 3 5 ns (min) RFS Rising Edge to SCLK Rising Edge Setup Time 5 t 3 5 ns (min) TFS Falling Edge to SCLK Falling Edge Setup Time 6 t 3 10 ns (max) SCLK Rising Edge to Data Out Valid 7 t 10 ns (min) DIN Data Valid to SCLK Falling Edge Setup Time 8 t 5 ns (min) DIN Data Valid after SCLK Falling Edge Hold Time 9 t 3, 4 20 ns (max) SCLK Rising Edge to D 10 OUT High Impedance t 100 ns (min) DOUT High Impedance to CONVST Falling Edge 11 NOTES 1Sample tested to ensure compliance. 2See Figures 16, 17 and 18. 3These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V DD = 5 V ± 10% and 0.4 V or 2 V for VDD = 3 V ± 10%. 4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 11, quoted in the Timing Characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances. Specifications subject to change without notice.
200
A IOL TO OUTPUT 2.1V PIN CL 50pF I 200
A OH
Figure 1. Load Circuit for Digital Output Timing Specifications REV. C –3– Document Outline Features General Description Product Highlights Functional Block Diagram Specifications Timing Characteristics Absolute Maximum Ratings ESD Caution Pin Configurations Pin Function Descriptions Terminology Signal to (Noise + Distortion) Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion Channel-to-Channel Isolation Relative Accuracy Differential Nonlinearity Offset Error Offset Error Match Gain Error Gain Error Match Track/Hold Acquisition Time Control Register (AD7811) Control Register (AD7812) Circuit Description Converter Operation Typical Connection Diagram Analog Input DC Acquisition Time AC Acquisition Time On-Chip Reference ADC Transfer Function Power-Down Options Power-On-Reset Power-Up Times Mode 2 Full Power-Down (PD1 = 1, PD0 = 0) Mode 2 Partial Power-Down (PD1 = 0, PD0 = 1) Power vs. Throughput Operating Modes Mode 1 Operation (High Speed Sampling) Mode 2 Operation (Automatic Power-Down) Serial Interface Simplifying the Serial Interface Microprocessor Interfacing AD7811/AD7812 to PIC16C6x/7x AD7811/AD7812 to MC68HC11 AD7811/AD7812 to 8051
