Datasheet AD7731 (Analog Devices) - 9

AD7731 PIN FUNCTION DESCRIPTIONS (Continued) Pin Pin No. Mnemonic Function
3 MCLK OUT When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK IN and MCLK OUT. If an external clock is applied to the MCLK IN, MCLK OUT provides an inverted clock signal. This clock can be used to provide a clock source for external circuits and MCLK OUT is capable of driving one CMOS load. 4 POL Clock Polarity. Logic Input. This determines the polarity of the serial clock. If the active edge for the proces- sor is a high-to-low SCLK transition, this input should be low. In this mode, the AD7731 puts out data on the DATA OUT line in a read operation on a low-to-high transition of SCLK and clocks in data from the DATA IN line in a write operation on a high-to-low transition of SCLK. In applications with a noncontinuous serial clock (such as most microcontroller applications), this means that the serial clock should idle low between data transfers. If the active edge for the processor is a low-to-high SCLK transition, this input should be high. In this mode, the AD7731 puts out data on the DATA OUT line in a read operation on a high-to-low transition of SCLK and clocks in data from the DATA IN line in a write operation on a low-to- high transition of SCLK. In applications with a noncontinuous serial clock (such as most microcontroller applications), this means that the serial clock should idle high between data transfers. 5 SYNC Logic Input that allows for synchronization of the digital filters and analog modulators when using a number of AD7731s. While SYNC is low, the nodes of the digital filter, the filter control logic and the calibration control logic are reset and the analog modulator is also held in its reset state. SYNC does not affect the digital interface but does reset RDY to a high state if it is low. While SYNC is asserted, the Mode Bits may be set up for a subsequent operation that will commence when the SYNC pin is deasserted. 6 RESET Logic Input. Active low input that resets the control logic, interface logic, digital filter, analog modulator and all on-chip registers of the part to power-on status. Effectively, everything on the part except for the clock oscillator is reset when the RESET pin is exercised. 7 NC No Connect. The user is advised not to connect anything to this pin. 8 AGND Ground reference point for analog circuitry. 9 AVDD Analog Positive Supply Voltage. The AVDD to AGND differential is 5 V nominal. 10 AIN1 Analog Input Channel 1. Programmable-gain analog input that can be used as a pseudo-differential input when used with AIN6 or as the positive input of a differential pair when used with AIN2. 11 AIN2 Analog Input Channel 2. Programmable-gain analog input that can be used as a pseudo-differential input when used with AIN6 or as the negative input of a differential pair when used with AIN1. 12 AIN3/D1 Analog Input Channel 3 or Digital Output 1. This pin can be used as either an analog input or a digital output bit as determined by the DEN bit of the Mode Register. When selected as a programmable-gain analog input, it can be used as a pseudo-differential input when used with AIN6 or as the positive input of a differential pair when used with AIN4. When selected as a digital output, this output can be programmed over the serial interface using bit D1 of the Mode Register. 13 AIN4/D0 Analog Input Channel 4 or Digital Output 0. This pin can be used as either an analog input or a digital output bit as determined by the DEN bit of the Mode Register. When selected as a programmable-gain analog input, it can be used as a pseudo-differential input when used with AIN6 or as the negative input of a differential pair when used with AIN3. When selected as a digital output, this output can be programmed over the serial interface using bit D0 of the Mode Register. 14 REF IN(+) Reference Input. Positive terminal of the differential reference input to the AD7731. REF IN(+) can lie anywhere between AVDD and AGND. The nominal reference voltage (i.e., the differential voltage between REF IN(+) and REF IN(–)) should be +2.5 V when the HIREF bit of the Mode Register is 0 and is +5 V when the HIREF bit of the Mode Register is 1. 15 REF IN(–) Reference Input. Negative terminal of the differential reference input to the AD7731. The REF IN(–) can lie anywhere between AVDD and AGND. 16 AIN5 Analog Input Channel 5. Programmable-gain analog input which can be used is the positive input of a differ- ential pair when used with AIN6. 17 AIN6 Analog Input Channel 6. Reference point for AIN1 through AIN4 in pseudo-differential mode or as the negative input of a differential input pair when used with AIN5. 18 STANDBY Logic Input. Taking this pin low shuts down the analog and digital circuitry, reducing current consumption to the 10 µA range. The on-chip registers retain all their values when the part is in standby mode. 19 CS Chip Select. Active low Logic Input used to select the AD7731. With this input hardwired low, the AD7731 can operate in its three-wire interface mode with SCLK, DIN and DOUT used to interface to the device. CS can be used to select the device in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the AD7731. –8– REV. 0 REV. A Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM AD7731-SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Ordering Guide ESD Caution PIN CONFIGURATION Pin Function Descriptions TERMINOLOGY OUTPUT NOISE AND RESOLUTION SPECIFICATION Output Noise (CHP = 0, SKIP= 1) Output Noise (CHP = 1, SKIP = 0) ON-CHIP REGISTERS Communications Register (RS2-RS0 = 0, 0, 0) Status Register (RS2-RS0 = 0, 0, 0); Power-On/Reset Status: CX Hex Data Register (RS2-RS0 = 0, 0, 1); Power On/Reset Status: 000000 Hex Mode Register (RS2-RS0 = 0, 1, 0); Power-On/Reset Status: 0174 Hex Filter Register (RS2-RS0 = 0, 1, 1); Power-On/Reset Status: 2002 Hex Offset Calibration Register (RS2-RS0 = 1, 0, 1) Gain Calibration Register (RS2-RS0 = 1, 1, 0) Test Register (RS2-RS0 = 1, 1, 1); Power On/Reset Status: 000000 Hex READING FROM AND WRITING TO THE ON-CHIP REGISTERS CALIBRATION OPERATION SUMMARY CIRCUIT DESCRIPTION ANALOG INPUT Analog Input Channels Buffered Inputs Analog Input Ranges Programmable Gain Amplifier Bipolar/Unipolar Inputs Burnout Currents REFERENCE INPUT Reference Detect SIGMA-DELTA MODULATOR DIGITAL FILTERING Filter Architecture First State Filter/SKIP Mode Enabled (SKIP =1) Nonchop Mode (SKIP =1, CHP = 0) Chop Mode (SKIP = 1, CHP =1) Second Stage Filter Normal FIR Operation (SKIP = 0) Chop Mode (SKIP = 0, CHP =1) Nonchop Mode (SKIP = 1, CHP = 0) FASTStep Mode (SKIP = 0, FAST = 1) CALIBRATION Internal Zero-Scale Calibration Internal Full-Scale Calibration System Zero-Scale Calibration System Full-Scale Calibration Span and Offset Limits Power-Up and Calibration Drift Considerations USING THE AD7731 Clocking and Oscillator Circuit System Synchronization Single-Shot Conversions Reset Input Standby Mode Digital Outputs POWER SUPPLIES Grounding and Layout Evaluting the AD7731 Performance SERIAL INTERFACE Write Operation Read Operation CONFIGURING THE AD7731 MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7731 to 68HC11 Interface AD7731 to 8051 Interface AD7731 to ADSP-2103/ADSP-2105 Interface APPLICATIONS Data Acquisition Programmable Logic Controllers Pressure Measurement Temperature Measurement Bipolar Input Signals PAGE INDEX TABLE INDEX OUTLINE DIMENSIONS