Datasheet AD7851 (Analog Devices) - 9

AD7851 TERMINOLOGY Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
Integral Nonlinearity
This is the maximum deviation from a straight line passing harmonics to the fundamental. For the AD7851, it is defined as through the endpoints of the ADC transfer function. The end- V ( 2 2 2 2 2 2 + V3 + V4 + V5 + V6 ) points of the transfer function are zero scale, a point 1/2 LSB THD(d ) B = 20log below the first code transition, and full scale, a point 1/2 LSB V1 above the last code transition. where V1 is the rms amplitude of the fundamental and V2, V3,
Differential Nonlinearity
V4, V5, and V6 are the rms amplitudes of the second through the This is the difference between the measured and the ideal 1 LSB sixth harmonics. change between any two adjacent codes in the ADC.
Peak Harmonic or Spurious Noise Total Unadjusted Error
Peak harmonic or spurious noise is defined as the ratio of the This is the deviation of the actual code from the ideal code tak- rms value of the next largest component in the ADC output ing all errors into account (gain, offset, integral nonlinearity, and spectrum (up to fS/2 and excluding dc) to the rms value of the other errors) at any point along the transfer function. fundamental. Normally, the value of this specification is deter-
Unipolar Offset Error
mined by the largest harmonic in the spectrum, but for parts This is the deviation of the first code transition (00 . 000 to where the harmonics are buried in the noise floor, it will be a 00 . 001) from the ideal AIN(+) voltage (AIN(–) + 1/2 LSB) noise peak. when operating in unipolar mode.
Intermodulation Distortion Positive Full-Scale Error
With inputs consisting of sine waves at two frequencies, fa and This applies to unipolar and bipolar modes and is the deviation of fb, any active device with nonlinearities will create distortion the last code transition from the ideal AIN(+) voltage (AIN(–) + products at sum and difference frequencies of mfa ± nfb where full scale – 1.5 LSB) after the offset error has been adjusted out. m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example,
Negative Full-Scale Error
the second-order terms include (fa + fb) and (fa – fb), while the This applies to bipolar mode only and is the deviation of the third-order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and first code transition (10 . 000 to 10 . 001) from the ideal (fa – 2fb). AIN(+) voltage (AIN(–) – VREF/2 + 0.5 LSB). Testing is performed using the CCIF standard where two
Bipolar Zero Error
input frequencies near the top end of the input bandwidth are This is the deviation of the midscale transition (all 1s to all 0s) used. In this case, the second-order terms are usually distanced from the ideal AIN(+) voltage (AIN(–) – 1/2 LSB). in frequency from the original sine waves while the third-order
Track-and-Hold Acquisition Time
terms are usually at a frequency close to the input frequencies. The track-and-hold amplifier returns into track mode at the end As a result, the second- and third-order terms are specified of conversion. Track-and-hold acquisition time is the time separately. The calculation of the intermodulation distortion is required for the output of the track-and-hold amplifier to reach as per the THD specification where it is the ratio of the rms its final value, within ± 1/2 LSB, after the end of conversion. sum of the individual distortion products to the rms amplitude
Signal-to-(Noise + Distortion) Ratio
of the sum of the fundamentals expressed in dBs. This is the measured ratio of signal-to-(noise + distortion) at
Power Supply Rejection Ratio (PSRR)
the output of the ADC. The signal is the rms amplitude of the PSRR is defined as the ratio of the power in ADC output at fre- fundamental. Noise is the sum of all nonfundamental signals up quency f to the power of the full-scale sine wave applied to the to half the sampling frequency (fS/2), excluding dc. The ratio is supply voltage (VDD). The units are in LSB, % of FS per % of dependent on the number of quantization levels in the digitiza- supply voltage, or expressed logarithmically, in dB (PSRR (dB) tion process; the more levels, the smaller the quantization noise. = 10 log (Pf/Pfs)). The theoretical signal-to-(noise + distortion) ratio for an ideal
Full Power Bandwidth (FPBW)
N-bit converter with a sine wave input is given by FPBW is that frequency at which the amplitude of the recon- Signal-to-(Noise + Distortion) = (6.02 N +1.76) dB structed fundamental (using FFTs and neglecting harmonics Thus, for a 14-bit converter, this is 86 dB. and SNR) is reduced by 3 dB for a full-scale input. –8– REV. B Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS SPECIFICATIONS TIMING SPECIFICATIONS TYPICAL TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS PINOUT FOR DIP, SOIC, AND SSOP ORDERING GUIDE TERMINOLOGY Integral Nonlinearity Differential Nonlinearity Total Unadjusted Error Unipolar Offset Error Positive Full-Scale Error Negative Full-Scale Error Bipolar Zero Error Track-and-Hold Acquisition Time Signal-to-(Noise + Distortion) Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion Power Supply Rejection Ratio (PSRR) Full Power Bandwidth (FPBW) PIN FUNCTION DESCRIPTIONS AD7851 ON-CHIP REGISTERS Addressing the On-Chip Registers Writing Reading CONTROL REGISTER STATUS REGISTER CALIBRATION REGISTERS Addressing the Calibration Registers Writing to/Reading from the Calibration Registers Adjusting the Offset Calibration Register Adjusting the Gain Calibration Register CIRCUIT INFORMATION CONVERTER DETAILS TYPICAL CONNECTION DIAGRAM ANALOG INPUT Acquisition Time DC/AC Applications Input Ranges Transfer Functions REFERENCE SECTION AD7851 PERFORMANCE CURVES POWER-DOWN OPTIONS POWER-UP TIMES Using an External Reference Using the Internal (On-Chip) Reference POWER VS. THROUGHPUT RATE CALIBRATION SECTION Calibration Overview Automatic Calibration on Power-On Self-Calibration Description Self-Calibration Timing System Calibration Description System Gain and Offset Interaction System Calibration Timing SERIAL INTERFACE SUMMARY Resetting the Serial Interface DETAILED TIMING SECTION Mode 1 (2-Wire 8051 Interface) Mode 2 (3-Wire SPI/QSPI Interface Mode) Mode 3 (QSPI Interface Mode) MODE 4 and 5 (Self-Clocking Modes) CONFIGURING THE AD7851 AD7851 as a Read-Only ADC Writing to the AD7851 Interface Modes 2 and 3 Configuration Interface Mode 1 Configuration Interface Modes 4 and 5 Configuration MICROPROCESSOR INTERFACING AD7851 to 8XC51/PIC17C42 Interface AD7851 to 68HC11/16/L11/PIC16C42 Interface AD7851 to ADSP-21xx Interface AD7851 to DSP56000/1/2/L002 Interface AD7851 to TMS320C20/25/5x/LC5x Interface APPLICATION HINTS Grounding and Layout Evaluating the AD7851 Performance AD785x Family OUTLINE DIMENSIONS Revision History