Datasheet AD9221, AD9223, AD9220 (Analog Devices) - 10

AD9221/AD9223/AD9220
The addition of a differential input structure gives the user an The SHA’s optimum distortion performance for a differential or additional level of flexibility that is not possible with traditional single-ended input is achieved under the following two conditions: flash converters. The input stage allows the user to easily config- (1) the common-mode voltage is centered around midsupply ure the inputs for either single-ended operation or differential (i.e., AVDD/2 or approximately 2.5 V) and (2) the input signal operation. The A/D’s input structure allows the dc offset of the voltage span of the SHA is set at its lowest (i.e., 2 V input span). input signal to be varied independently of the input span of the This is due to the sampling switches, QS1, being CMOS switches converter. Specifically, the input to the A/D core is the differ- whose RON resistance is very low but has some signal depen- ence of the voltages applied at the VINA and VINB input dency that causes frequency dependent ac distortion while the pins. Therefore, the equation, SHA is in the track mode. The RON resistance of a CMOS (1) switch is typically lowest at its midsupply but increases symmetri- V =VINA –VINB CORE cally as the input signal approaches either AVDD or AVSS. A defines the output of the differential input stage and provides lower input signal voltage span centered at midsupply reduces the input to the A/D core. the degree of RON modulation. The voltage, VCORE, must satisfy the condition, Figure 6 compares the AD9221/AD9223/AD9220’s THD vs. (2) frequency performance for a 2 V input span with a common- –VREF ≤V ≤VREF CORE mode voltage of 1 V and 2.5 V. Note how each A/D with a where VREF is the voltage at the VREF pin. common-mode voltage of 1 V exhibits a similar degradation in While an infinite combination of VINA and VINB inputs exist THD performance at higher frequencies (i.e., beyond 750 kHz). that satisfy Equation 2, there is an additional limitation placed Similarly, note how the THD performance at lower frequencies on the inputs by the power supply voltages of the AD9221/ becomes less sensitive to the common-mode voltage. As the AD9223/AD9220. The power supplies bound the valid operat- input frequency approaches dc, the distortion will be dominated ing range for VINA and VINB. The condition, by static nonlinearities such as INL and DNL. It is important to note that these dc static nonlinearities are independent of any AVSS – . 0 3V <VINA < AVDD + . 0 3V (3) RON modulation. AVSS – . 0 3V <VINB < AVDD + . 0 3V where AVSS is nominally 0 V and AVDD is nominally 5 V,
–50
defines this requirement. Thus, the range of valid inputs for VINA and VINB is any combination that satisfies both
AD9220 1VCM
Equations 2 and 3.
–60
For additional information showing the relationship between
AD9223
VINA, VINB, VREF and the digital output of the AD9221/
1V AD9221 CM
AD9223/AD9220, see Table IV.
1V –70 CM
Refer to Table I and Table II at the end of this section for a
THD – dB AD9223
summary of both the various analog input and reference con-
2.5VCM
figurations.
–80 AD9221 AD9220 ANALOG INPUT OPERATION 2.5V 2.5V CM CM
Figure 5 shows the equivalent analog input of the AD9221/
–90
AD9223/AD9220, which consists of a differential sample-and-
0.1 1 10 FREQUENCY – MHz
hold amplifier (SHA). The differential input structure of the SHA is highly flexible, allowing the devices to be easily config- Figure 6. AD9221/AD9223/AD9220 THD vs. Frequency for ured for either a differential or single-ended input. The dc VCM = 2.5 V and 1.0 V (AIN = –0.5 dB, Input Span = 2.0 V p-p) offset, or common-mode voltage, of the input(s) can be set to Due to the high degree of symmetry within the SHA topology, a accommodate either single-supply or dual-supply systems. Also, significant improvement in distortion performance for differen- note that the analog inputs, VINA and VINB, are interchange- tial input signals with frequencies up to and beyond Nyquist can able with the exception that reversing the inputs to the VINA be realized. This inherent symmetry provides excellent cancella- and VINB pins results in a polarity inversion. tion of both common-mode distortion and noise. Also, the required input signal voltage span is reduced by a half, which
CH
further reduces the degree of RON modulation and its effects
Q
on distortion.
S2 C + PIN Q C
The optimum noise and dc linearity performance for either
C S1 S PAR VINA
differential or single-ended inputs is achieved with the largest
Q Q C H1 S1 S
input signal voltage span (i.e., 5 V input span) and matched
VINB C –
input impedance for VINA and VINB. Note that only a slight
PIN Q C S2 PAR
degradation in dc linearity performance exists between the 2 V and 5 V input span as specified in the AD9221/AD9223/
CH
AD9220 DC Specifications. Figure 5. AD9221/AD9223/AD9220 Simplified Input Circuit –10– REV. E Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS DEFINITIONS OF SPECIFICATIONS Integral Nonlinearity (INL) Differential Nonlinearity (DNL, No Missing Codes) Zero Error Gain Error Temperature Drift Power Supply Rejection Aperture Jitter Aperture Delay Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Signal-to-Noise Ratio (SNR) Spurious Free Dynamic Range (SFDR) Typical Performance Characteristics INTRODUCTION ANALOG INPUT AND REFERENCE OVERVIEW ANALOG INPUT OPERATION REFERENCE OPERATION DRIVING THE ANALOG INPUTS Introduction SINGLE-ENDED MODE OF OPERATION DC COUPLING AND INTERFACE ISSUES Simple Op Amp Buffer Op Amp with DC Level Shifting AC COUPLING AND INTERFACE ISSUES Simple AC Interface Alternative AC Interface Op Amp Selection Guide DIFFERENTIAL MODE OF OPERATION REFERENCE CONFIGURATIONS USING THE INTERNAL REFERENCE Single-Ended Input with 0 to 2 VREF Range Single-Ended or Differential Input, VCM = 2.5 V VINA Resistor Programmable Reference USING AN EXTERNAL REFERENCE Variable Input Span with VCM = 2.5 V Single-Ended Input with 0 to 2 VREF Range Low Cost/Power Reference DIGITAL INPUTS AND OUTPUTS Digital Outputs Out Of Range (OTR) Digital Output Driver Considerations (DVDD) Clock Input and Considerations GROUNDING AND DECOUPLING Analog and Digital Grounding Analog and Digital Supply Decoupling APPLICATIONS Direct IF Down Conversion Using the AD9220 Multichannel Data Acquisition with Autocalibration OUTLINE DIMENSIONS Revision History