Datasheet AD7861 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 11-Bit Resolution Simultaneous Sampling ADC |
| Pages / Page | 7 / 6 — AD7861. ANALOG INPUT BLOCK. Channel Selected. DIGITAL INTERFACE. REGISTER … |
| Revision | B |
| File Format / Size | PDF / 126 Kb |
| Document Language | English |
AD7861. ANALOG INPUT BLOCK. Channel Selected. DIGITAL INTERFACE. REGISTER BASED INPUT/OUTPUT. BUSY. REGISTER ADDRESSING
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Text Version of Document
AD7861 ANALOG INPUT BLOCK
The user must select which channels to convert using M0/M1, a The AD7861 is an 11-bit resolution, successive approximation minimum of two clock cycles before the start of conversion. analog-to-digital (A/D) converter with twos complement output The AD7861 provides 4 auxiliary input channels which can be data format. The analog input range is 0 V–5 V with a 2.5 V individually multiplexed into the auxiliary ADC channel. Pins S0/ reference as defined by the reference input pin (REFIN). The S1 are used to multiplex these auxiliary channels according to the AD7861 has an internal 2.5 V ± 5% reference, which is utilized following table. It is important to note that the ADC performs a by connecting the reference output pin (REFOUT) to the series of conversions based on the input voltage on each pin REFIN pin. (including the AUX pin) at the start of the CONVST conversion The A/D conversion time is determined by the system clock pulse. The user must select the auxiliary channel using S0/S1 frequency, which can range from 6.25 MHz to 12.5 MHz. a minimum of two clock cycles before the start of the conversion Forty clock cycles are required to complete each conversion. sequence. There is a 4-channel simultaneous sample and hold amplifier (SHA) at the AD7861 input stage. This allows up to 4 channels to
S1 S0 Channel Selected
be simultaneously held and sequentially digitized. The SHA acquisition time is 20 clock cycles and is independent of the 0 0 AUX0 number of channels sampled. 0 1 AUX1 1 0 AUX2 The minimum throughput time can be calculated as follows: 1 1 AUX3 t = t + (n × t ) AA SHA CONV where tAA = analog acquisition time, tSHA = SHA acquisition
DIGITAL INTERFACE
time, n = # channels, tCONV = conversion time per channel The AD7861 is designed to interface with the ADSP-21xx (40 clock cycles). family of DSPs. The 12-bit parallel interface can also be used A/D conversions are initiated by an external analog sample with other DSPs and microcontrollers. clock pin (CONVST). The 11-bit A/D conversion output occupies the 11 most The CONVST input can be run asynchronous to the AD7861 significant bits of the 12-bit interface. The LSB (Data Bit 0) is system clock. When CONVST is run asynchronous from CLK, tied low. the falling edge of CLK subsequent to CONVST high initiates
REGISTER BASED INPUT/OUTPUT
the conversion. To facilitate integration into most designs, a register based
BUSY
input/output structure is provided. These registers can be The AD7861 BUSY pin goes low at the start of conversion, and memory mapped into the user’s system along with other remains low for 40 clock cycles per channel. When BUSY goes memory mapped peripherals. high, this indicates that the output data buffers have been
REGISTER ADDRESSING
updated. Data from the previous conversion can be read up to Two address lines (A0 through A1) are used in conjunction with (n × 40 – 1) clock cycles after the start of conversion (n = control lines (CS, RD) to select registers VIN1, VIN2, VIN3, or number of channels converted). Refer to Figure 3. AUX. These control lines are active low. Timing and logical sense is as for the ADSP-2100 family.
t = (n x 40 –1) CLOCK CYCLES t = 1 CLOCK CYCLE t = n x 40 CLOCK CYCLES Pin Function CLK (n x 40 –1) CLOCK CYCLES
CS Enables the AD7861 Register Interface RD Places the Internal Register on the Data Bus
BUSY REGISTER LISTING CONVST
The output of each channel is stored in its respective register. The symbolic names and address locations are listed in the
OLD DATA VALID NEW DATA VALID DATA
following table. Figure 3. Busy Pulse Timing
Name A1 A0 Register Function CHANNEL SELECTION
Determining which channels are converted is dependent on the VIN1 0 0 A/D Conversion Result Channel VIN1 settings of M0 and M1. The available channel combinations are: VIN2 0 1 A/D Conversion Result Channel VIN2 VIN3 1 0 A/D Conversion Result Channel VIN3
M1 M0 Channels Converted
AUX 1 1 A/D Conversion Result Channel AUX 0 0 VIN2, VIN3 0 1 VIN2, VIN3, AUX 1 0 VIN1, VIN2, VIN3 1 1 VIN1, VIN2, VIN3, AUX REV. B –5–
The user must select which channels to convert using M0/M1, a The AD7861 is an 11-bit resolution, successive approximation minimum of two clock cycles before the start of conversion. analog-to-digital (A/D) converter with twos complement output The AD7861 provides 4 auxiliary input channels which can be data format. The analog input range is 0 V–5 V with a 2.5 V individually multiplexed into the auxiliary ADC channel. Pins S0/ reference as defined by the reference input pin (REFIN). The S1 are used to multiplex these auxiliary channels according to the AD7861 has an internal 2.5 V ± 5% reference, which is utilized following table. It is important to note that the ADC performs a by connecting the reference output pin (REFOUT) to the series of conversions based on the input voltage on each pin REFIN pin. (including the AUX pin) at the start of the CONVST conversion The A/D conversion time is determined by the system clock pulse. The user must select the auxiliary channel using S0/S1 frequency, which can range from 6.25 MHz to 12.5 MHz. a minimum of two clock cycles before the start of the conversion Forty clock cycles are required to complete each conversion. sequence. There is a 4-channel simultaneous sample and hold amplifier (SHA) at the AD7861 input stage. This allows up to 4 channels to
S1 S0 Channel Selected
be simultaneously held and sequentially digitized. The SHA acquisition time is 20 clock cycles and is independent of the 0 0 AUX0 number of channels sampled. 0 1 AUX1 1 0 AUX2 The minimum throughput time can be calculated as follows: 1 1 AUX3 t = t + (n × t ) AA SHA CONV where tAA = analog acquisition time, tSHA = SHA acquisition
DIGITAL INTERFACE
time, n = # channels, tCONV = conversion time per channel The AD7861 is designed to interface with the ADSP-21xx (40 clock cycles). family of DSPs. The 12-bit parallel interface can also be used A/D conversions are initiated by an external analog sample with other DSPs and microcontrollers. clock pin (CONVST). The 11-bit A/D conversion output occupies the 11 most The CONVST input can be run asynchronous to the AD7861 significant bits of the 12-bit interface. The LSB (Data Bit 0) is system clock. When CONVST is run asynchronous from CLK, tied low. the falling edge of CLK subsequent to CONVST high initiates
REGISTER BASED INPUT/OUTPUT
the conversion. To facilitate integration into most designs, a register based
BUSY
input/output structure is provided. These registers can be The AD7861 BUSY pin goes low at the start of conversion, and memory mapped into the user’s system along with other remains low for 40 clock cycles per channel. When BUSY goes memory mapped peripherals. high, this indicates that the output data buffers have been
REGISTER ADDRESSING
updated. Data from the previous conversion can be read up to Two address lines (A0 through A1) are used in conjunction with (n × 40 – 1) clock cycles after the start of conversion (n = control lines (CS, RD) to select registers VIN1, VIN2, VIN3, or number of channels converted). Refer to Figure 3. AUX. These control lines are active low. Timing and logical sense is as for the ADSP-2100 family.
t = (n x 40 –1) CLOCK CYCLES t = 1 CLOCK CYCLE t = n x 40 CLOCK CYCLES Pin Function CLK (n x 40 –1) CLOCK CYCLES
CS Enables the AD7861 Register Interface RD Places the Internal Register on the Data Bus
BUSY REGISTER LISTING CONVST
The output of each channel is stored in its respective register. The symbolic names and address locations are listed in the
OLD DATA VALID NEW DATA VALID DATA
following table. Figure 3. Busy Pulse Timing
Name A1 A0 Register Function CHANNEL SELECTION
Determining which channels are converted is dependent on the VIN1 0 0 A/D Conversion Result Channel VIN1 settings of M0 and M1. The available channel combinations are: VIN2 0 1 A/D Conversion Result Channel VIN2 VIN3 1 0 A/D Conversion Result Channel VIN3
M1 M0 Channels Converted
AUX 1 1 A/D Conversion Result Channel AUX 0 0 VIN2, VIN3 0 1 VIN2, VIN3, AUX 1 0 VIN1, VIN2, VIN3 1 1 VIN1, VIN2, VIN3, AUX REV. B –5–
