Datasheet AD7713 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | CMOS, Low Power 24-Bit Sigma-Delta, Signal Conditioning ADC with Matched RTD Current Sources |
| Pages / Page | 29 / 3 — AD7713–SPECIFICATIONS (AVDD = 5 V. 5%; DVDD = 5 V. 5%; REF IN(+) = 2.5 V; … |
| Revision | D |
| File Format / Size | PDF / 333 Kb |
| Document Language | English |
AD7713–SPECIFICATIONS (AVDD = 5 V. 5%; DVDD = 5 V. 5%; REF IN(+) = 2.5 V; REF IN(–) = AGND;
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Text Version of Document
AD7713–SPECIFICATIONS (AVDD = 5 V
ⴞ
5%; DVDD = 5 V
ⴞ
5%; REF IN(+) = 2.5 V; REF IN(–) = AGND; MCLK IN = 2 MHz, unless otherwise noted. All specifications TMIN to TMAX, unless otherwise noted.) Parameter A, S Versions1 Unit Conditions/Comments
STATIC PERFORMANCE No Missing Codes 24 Bits min Guaranteed by Design. For Filter Notches ≤ 12 Hz. 22 Bits min For Filter Notch = 20 Hz. 18 Bits min For Filter Notch = 50 Hz. 15 Bits min For Filter Notch = 100 Hz. 12 Bits min For Filter Notch = 200 Hz. Output Noise See Tables I and II Depends on Filter Cutoffs and Selected Gain. Integral Nonlinearity ±0.0015 % of FSR max Filter Notches ≤ 12 Hz; Typically ± 0.0003%. Positive Full-Scale Error2, 3, 4 Full-Scale Drift5 1 µV/°C typ For Gains of 1, 2. 0.3 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128. Unipolar Offset Error2, 4 Unipolar Offset Drift5 0.5 µV/°C typ For Gains of 1, 2. 0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128. Bipolar Zero Error2, 4 Bipolar Zero Drift5 0.5 µV/°C typ For Gains of 1, 2. 0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128. Gain Drift 2 ppm/°C typ Bipolar Negative Full-Scale Error2 ±0.0004 % of FSR max Typically ± 0.0006%. Bipolar Negative Full-Scale Drift5 1 µV/°C typ For Gains of 1, 2. 0.3 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128. ANALOG INPUTS Input Sampling Rate, fS See Table III Normal-Mode 50 Hz Rejection6 100 dB min For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz, ± 0.02 ⫻ fNOTCH. Normal-Mode 60 Hz Rejection6 100 dB min For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz, ± 0.02 ⫻ fNOTCH. AIN1, AIN27 Input Voltage Range8 For Normal Operation. Depends on Gain Selected. 0 to +V 9 REF V max Unipolar Input Range (B/U Bit of Control Register = 1). ±VREF V max Bipolar Input Range (B/U Bit of Control Register = 0). Common-Mode Rejection (CMR) 100 dB min At dc and AVDD = 5 V. 90 dB min At dc and AVDD = 10 V. Common-Mode 50 Hz Rejection6 150 dB min For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz, ± 0.02 ⫻ fNOTCH. Common-Mode 60 Hz Rejection6 150 dB min For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz, ± 0.02 ⫻ fNOTCH. Common-Mode Voltage Range10 AGND to AVDD V min to V max DC Input Leakage Current @ 25°C 10 pA max TMIN to TMAX 1 nA max Sampling Capacitance6 20 pF max AIN3 Input Voltage Range 0 to + 4 ⫻ VREF V max For Normal Operation. Depends on Gain Selected. Gain Error11 ±0.05 % typ Additional Error Contributed by Resistor Attenuator. Gain Drift 1 ppm/°C typ Additional Drift Contributed by Resistor Attenuator. Offset Error11 4 mV max Additional Error Contributed by Resistor Attenuator. Input Impedance 30 kΩ min –2– REV. D Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTION TERMINOLOGY Integral Nonlinearity Positive Full-Scale Error Unipolar Offset Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span CONTROL REGISTER (24 BITS) Filter Selection (FS11 to FS0) CIRCUIT DESCRIPTION THEORY OF OPERATION Input Sample Rate DIGITAL FILTERING Filter Characteristics Post Filtering Antialias Considerations ANALOG INPUT FUNCTIONS Analog Input Ranges Burn Out Current RTD Excitation Currents Bipolar/Unipolar Inputs REFERENCE INPUT USING THE AD7713 SYSTEM DESIGN CONSIDERATIONS Clocking System Synchronization Accuracy Autocalibration Self-Calibration System Calibration System Offset Calibration Background Calibration Span and Offset Limits POWER-UP AND CALIBRATION Drift Considerations POWER SUPPLIES AND GROUNDING DIGITAL INTERFACE Self-Clocking Mode Read Operation Write Operation External Clocking Mode Read Operation Write Operation SIMPLIFYING THE EXTERNAL CLOCKING MODE INTERFACE MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7713 to 8XC51 Interface AD7713 to 68HC11 Interface APPLICATIONS 4-Wire RTD Configurations 3-Wire RTD Configurations 4–20 mA Loop OTHER 24-BIT SIGNAL CONDITIONING ADCS AVAILABLE FROM ANALOG DEVICES AD7710 AD7711 AD7712 OUTLINE DIMENSIONS Revision History
ⴞ
5%; DVDD = 5 V
ⴞ
5%; REF IN(+) = 2.5 V; REF IN(–) = AGND; MCLK IN = 2 MHz, unless otherwise noted. All specifications TMIN to TMAX, unless otherwise noted.) Parameter A, S Versions1 Unit Conditions/Comments
STATIC PERFORMANCE No Missing Codes 24 Bits min Guaranteed by Design. For Filter Notches ≤ 12 Hz. 22 Bits min For Filter Notch = 20 Hz. 18 Bits min For Filter Notch = 50 Hz. 15 Bits min For Filter Notch = 100 Hz. 12 Bits min For Filter Notch = 200 Hz. Output Noise See Tables I and II Depends on Filter Cutoffs and Selected Gain. Integral Nonlinearity ±0.0015 % of FSR max Filter Notches ≤ 12 Hz; Typically ± 0.0003%. Positive Full-Scale Error2, 3, 4 Full-Scale Drift5 1 µV/°C typ For Gains of 1, 2. 0.3 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128. Unipolar Offset Error2, 4 Unipolar Offset Drift5 0.5 µV/°C typ For Gains of 1, 2. 0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128. Bipolar Zero Error2, 4 Bipolar Zero Drift5 0.5 µV/°C typ For Gains of 1, 2. 0.25 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128. Gain Drift 2 ppm/°C typ Bipolar Negative Full-Scale Error2 ±0.0004 % of FSR max Typically ± 0.0006%. Bipolar Negative Full-Scale Drift5 1 µV/°C typ For Gains of 1, 2. 0.3 µV/°C typ For Gains of 4, 8, 16, 32, 64, 128. ANALOG INPUTS Input Sampling Rate, fS See Table III Normal-Mode 50 Hz Rejection6 100 dB min For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz, ± 0.02 ⫻ fNOTCH. Normal-Mode 60 Hz Rejection6 100 dB min For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz, ± 0.02 ⫻ fNOTCH. AIN1, AIN27 Input Voltage Range8 For Normal Operation. Depends on Gain Selected. 0 to +V 9 REF V max Unipolar Input Range (B/U Bit of Control Register = 1). ±VREF V max Bipolar Input Range (B/U Bit of Control Register = 0). Common-Mode Rejection (CMR) 100 dB min At dc and AVDD = 5 V. 90 dB min At dc and AVDD = 10 V. Common-Mode 50 Hz Rejection6 150 dB min For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz, ± 0.02 ⫻ fNOTCH. Common-Mode 60 Hz Rejection6 150 dB min For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz, ± 0.02 ⫻ fNOTCH. Common-Mode Voltage Range10 AGND to AVDD V min to V max DC Input Leakage Current @ 25°C 10 pA max TMIN to TMAX 1 nA max Sampling Capacitance6 20 pF max AIN3 Input Voltage Range 0 to + 4 ⫻ VREF V max For Normal Operation. Depends on Gain Selected. Gain Error11 ±0.05 % typ Additional Error Contributed by Resistor Attenuator. Gain Drift 1 ppm/°C typ Additional Drift Contributed by Resistor Attenuator. Offset Error11 4 mV max Additional Error Contributed by Resistor Attenuator. Input Impedance 30 kΩ min –2– REV. D Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTION TERMINOLOGY Integral Nonlinearity Positive Full-Scale Error Unipolar Offset Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span CONTROL REGISTER (24 BITS) Filter Selection (FS11 to FS0) CIRCUIT DESCRIPTION THEORY OF OPERATION Input Sample Rate DIGITAL FILTERING Filter Characteristics Post Filtering Antialias Considerations ANALOG INPUT FUNCTIONS Analog Input Ranges Burn Out Current RTD Excitation Currents Bipolar/Unipolar Inputs REFERENCE INPUT USING THE AD7713 SYSTEM DESIGN CONSIDERATIONS Clocking System Synchronization Accuracy Autocalibration Self-Calibration System Calibration System Offset Calibration Background Calibration Span and Offset Limits POWER-UP AND CALIBRATION Drift Considerations POWER SUPPLIES AND GROUNDING DIGITAL INTERFACE Self-Clocking Mode Read Operation Write Operation External Clocking Mode Read Operation Write Operation SIMPLIFYING THE EXTERNAL CLOCKING MODE INTERFACE MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7713 to 8XC51 Interface AD7713 to 68HC11 Interface APPLICATIONS 4-Wire RTD Configurations 3-Wire RTD Configurations 4–20 mA Loop OTHER 24-BIT SIGNAL CONDITIONING ADCS AVAILABLE FROM ANALOG DEVICES AD7710 AD7711 AD7712 OUTLINE DIMENSIONS Revision History
