Datasheet AD7880 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | CMOS, Single +5 V Supply, Low Power, 12-Bit Sampling ADC |
| Pages / Page | 17 / 5 — AD7880. ORDERING GUIDE. PIN CONFIGURATION. Bipolar. Full-Scale. Zero. … |
| File Format / Size | PDF / 375 Kb |
| Document Language | English |
AD7880. ORDERING GUIDE. PIN CONFIGURATION. Bipolar. Full-Scale. Zero. INA. 24 VDD. Temperature. Error. Package. VINB 2. 23 MODE. Model. Range. (LSBs)
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AD7880 ORDERING GUIDE PIN CONFIGURATION Bipolar V Full-Scale Zero INA 1 24 VDD Temperature Error Error Package VINB 2 23 MODE Model Range (LSBs) (LSBs) Option* 3 22 AGND DB11
AD7880BN –40°C to +85°C ±15 ±10 N-24
VREF 4 21 DB10
AD7880BQ –40°C to +85°C ±15 ±10 Q-24
CS 5 20 DB9
AD7880CN –40°C to +85°C ± 5 ± 5 N-24
AD7880 CONVST 6 19
AD7880CQ –40°C to +85°C ± 5 ± 5 Q-24
DB8 TOP VIEW
AD7880BR –40°C to +85°C ±15 ±10 R-24
RD 7 (Not to Scale) 18 DB7
AD7880CR –40°C to +85°C ± 5 ± 5 R-24
BUSY 8 17 DB6
*N = Plastic DIP; Q = Cerdip; R = SOIC (Small Outline Integrated Circuit).
9 CLKIN 16 DB5 10 DGND 15 DB4 DB0 11 14 DB3 12 DB1 13 DB2 PIN FUNCTION DESCRIPTION Pin Pin No. Mnemonic Function
1 VINA Analog Input. 2 VINB Analog Input. 3 AGND Analog Ground. 4 VREF Voltage Reference Input. This is normally tied to VDD. 5 CS Chip Select. Active Low Logic input. The device is selected when this input is active. 6 CONVST Convert Start. A low to high transition on this input puts the track/hold into hold mode and starts con- version. This input is asynchronous to the CLKIN and is independent of CS and RD. 7 RD Read. Active Low Logic Input. This input is used in conjunction with CS low to enable data outputs. 8 BUSY Active Low Logic Output. This status line indicates converter status. BUSY is low during conversion. 9 CLKIN Clock Input. TTL-compatible logic input. Used as the clock source for the A/D converter. The mark/ space ratio of the clock can vary from 40/60 to 60/40. 10 DGND Digital Ground. 11 . 22 DB0–DB11 Three-State Data Outputs. These become active when CS and RD are brought low. 23 MODE MODE Input. This input is used to put the device into the power save mode (MODE = 0 V). During normal operation, the MODE input will be a logic high (MODE = VDD). 24 VDD Power Supply. This is nominally +5 V. –4– REV. 0
AD7880BN –40°C to +85°C ±15 ±10 N-24
VREF 4 21 DB10
AD7880BQ –40°C to +85°C ±15 ±10 Q-24
CS 5 20 DB9
AD7880CN –40°C to +85°C ± 5 ± 5 N-24
AD7880 CONVST 6 19
AD7880CQ –40°C to +85°C ± 5 ± 5 Q-24
DB8 TOP VIEW
AD7880BR –40°C to +85°C ±15 ±10 R-24
RD 7 (Not to Scale) 18 DB7
AD7880CR –40°C to +85°C ± 5 ± 5 R-24
BUSY 8 17 DB6
*N = Plastic DIP; Q = Cerdip; R = SOIC (Small Outline Integrated Circuit).
9 CLKIN 16 DB5 10 DGND 15 DB4 DB0 11 14 DB3 12 DB1 13 DB2 PIN FUNCTION DESCRIPTION Pin Pin No. Mnemonic Function
1 VINA Analog Input. 2 VINB Analog Input. 3 AGND Analog Ground. 4 VREF Voltage Reference Input. This is normally tied to VDD. 5 CS Chip Select. Active Low Logic input. The device is selected when this input is active. 6 CONVST Convert Start. A low to high transition on this input puts the track/hold into hold mode and starts con- version. This input is asynchronous to the CLKIN and is independent of CS and RD. 7 RD Read. Active Low Logic Input. This input is used in conjunction with CS low to enable data outputs. 8 BUSY Active Low Logic Output. This status line indicates converter status. BUSY is low during conversion. 9 CLKIN Clock Input. TTL-compatible logic input. Used as the clock source for the A/D converter. The mark/ space ratio of the clock can vary from 40/60 to 60/40. 10 DGND Digital Ground. 11 . 22 DB0–DB11 Three-State Data Outputs. These become active when CS and RD are brought low. 23 MODE MODE Input. This input is used to put the device into the power save mode (MODE = 0 V). During normal operation, the MODE input will be a logic high (MODE = VDD). 24 VDD Power Supply. This is nominally +5 V. –4– REV. 0
