Datasheet AD5383 (Analog Devices) - 2

AD5383* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS DESIGN RESOURCES
View a parametric search of comparable parts. • AD5383 Material Declaration • PCN-PDN Information
DOCUMENTATION
• Quality And Reliability
Application Notes
• Symbols and Footprints • An-1228: 32 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using the
DISCUSSIONS
AD5383 DAC View all AD5383 EngineerZone Discussions. • AN-1229: AD5383 Channel Monitor Function • AN-214: Ground Rules for High Speed Circuits
SAMPLE AND BUY Data Sheet
Visit the product page to see pricing options. • AD5383: 32-Channel, 3 V/5 V, Single-Supply, 12-Bit, denseDAC Data Sheet
TECHNICAL SUPPORT Product Highlight
Submit a technical question or find your regional support • Extending the denseDAC™ Multichannel D/As number.
SOFTWARE AND SYSTEMS REQUIREMENTS DOCUMENT FEEDBACK
• AD5380 IIO Multi-Channel DAC Linux Driver Submit feedback for this data sheet.
REFERENCE MATERIALS Solutions Bulletins & Brochures
• Digital to Analog Converters ICs Solutions Bulletin
Technical Articles
• Software Calibration Reduces D/A Converter Offset and Gain Errors
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
Document Outline Features Integrated Functions Applications Functional Block Diagram Table of Contents Revision History General Description Specifications AD5383-5 Specifications AD5383-3 Specifications AC Characteristics9F Timing Characteristics Serial Interface Timing I2C Serial Interface Timing Parallel Interface Timing Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Functional Description DAC Architecture—General Data Decoding On-Chip Special Function Registers (SFR) SFR Commands NOP (No Operation) Write CLR Code Soft CLR Soft Power-Down Soft Power-Up Soft RESET Control Register Write/Read Channel Monitor Function Hardware Functions Reset Function Asynchronous Clear Function BUSY\ and LDAC\ Functions FIFO Operation in Parallel Mode Power-On Reset Power-Down Interfaces DSP-, SPI-, MICROWIRE-Compatible Serial Interfaces Standalone Mode Daisy-Chain Mode Readback Mode I2C Serial Interface I2C Data Transfer START and STOP Conditions Repeated START Conditions Acknowledge Bit (ACK) AD5383 Slave Addresses Write Operation 4-Byte Mode 3-Byte Mode 2-Byte Mode Parallel Interface CS\ Pin WR\ Pin REG0, REG1 Pins Pins A4 to A0 Pins DB11 to DB0 Microprocessor Interfacing Parallel Interface AD5383 to MC68HC11 AD5383 to PIC16C6x/7x AD5383 to 8051 AD5383 to ADSP-BF527 Applications Information Power Supply Decoupling Power Supply Sequencing Typical Configuration Circuit Channel Monitor Function Toggle Mode Function Thermal Monitor Function Optical Attenuators Utilizing the FIFO Outline Dimensions Ordering Guide