Datasheet AD526 (Analog Devices) - 10

AD526 TIMING AND CONTROL DIGITAL FEEDTHROUGH
With either CS or CLK or both held high, the AD526 gain state
Table I. Logic Input Truth Table
will remain constant regardless of the transitions at the A0, A1, A2 or B inputs. However, high speed logic transitions will un-
Gain Code Control Condition
avoidably feed through to the analog circuitry within the AD526
A2 A1 A0 B CLK (CS = 0) Gain Condition
causing spikes to occur at the signal output. X X X X 1 Previous State Latched This feedthrough effect can be completely eliminated by operat- 0 0 0 1 0 1 Transparent ing the AD526 in the transparent mode and latching the gain 0 0 1 1 0 2 Transparent code in an external bank of latches (Figure 36). 0 1 0 1 0 4 Transparent To operate the AD526 using serial inputs, the configuration 0 1 1 1 0 8 Transparent shown in Figure 36 can be used with the 74LS174 replaced by a 1 X X 1 0 16 Transparent serial-in/parallel-out latch, such as the 54LS594. X X X 0 0 1 Transparent X X X 0 1 1 Latched
A1 A0 A2 B +5V
0 0 0 1 1 1 Latched 0 0 1 1 1 2 Latched
1
m
F
0 1 0 1 1 4 Latched
TIMING 74LS174 SIGNAL
0 1 1 1 1 8 Latched 1 X X 1 1 16 Latched
+VS
NOTE: X = Don’t Care.
0.1
m
F
The specifications on page 3, in combination with Figure 35, give the timing requirements for loading new gain codes.
OUT 16 15 14 13 12 11 10 9 FORCE A1 A0 CS CLK A2 B GAIN CODE LOGIC AND LATCHES VALID DATA INPUTS 16 8 4 2 1 TC VOUT GAIN NETWORK CLK OR CS – T T S H AD526 + TC = MINIMUM CLOCK CYCLE NOTE: THRESHOLD LEVEL FOR 1 2 3 4 5 6 7 8 OUT T GAIN CODE, CS, AND CLK IS 1.4V. S = DATA SETUP TIME SENSE TH = DATA HOLD TIME 0.1
m
F V
Figure 35. AD526 Timing
IN –VS
Figure 36. Using an External Latch to Minimize Digital Feedthrough REV. D –9–