Datasheet MCP651, MCP651S, MCP652, MCP653, MCP654, MCP655, MCP659 (Microchip) - 6

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MCP651/1S/2/3/4/5/9 TABLE 1-4: TEMPERATURE SPECIFICATIONS Electrical Characteristics:
Unless otherwise indicated, all limits are specified for: VDD = +2.5V to +5.5V, VSS = GND.
Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges
Specified Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C
(Note 1 )
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-2×3 SOT JA — 220.7 — °C/W Thermal Resistance, 6L-2×3 SOT JA — 190.5 — °C/W Thermal Resistance, 8L-2×3 TDFN JA — 52.5 — °C/W Thermal Resistance, 8L-3×3 DFN JA — 63 — °C/W
(Note 2 )
Thermal Resistance, 8L-SOIC JA — 163 — °C/W Thermal Resistance, 10L-3×3 DFN JA — 71 — °C/W
(Note 2 )
Thermal Resistance, 10L-MSOP JA — 202 — °C/W Thermal Resistance, 14L-SOIC JA — 95.3 — °C/W Thermal Resistance, 14L-TSSOP JA — 100 — °C/W Thermal Resistance, 16L-4x4-QFN JA — 46 — °C/W
(Note 2 ) Note 1:
Operation must not cause TJ to exceed Maximum Junction Temperature specification (150°C).
2:
Measured on a standard JC51-7, four-layer printed circuit board with ground plane and vias.
1.3 Timing Diagram
CAL/CS VIH VIL VDD VPRH VPRL tCSU tPON t t COFF tCON POFF V High Z OUT High Z On On High Z I -3 µA (typical) -6 mA (typical) SS -3 µA (typical) -6 mA (typical) -3 µA (typical) ICS 0 nA (typical) 0.7 µA (typical) 0 nA (typical)
Note
: For the MCP655 dual and the MCP659 quad, there is an additional constraint on toggling the two CAL/CS pins close together; see the T specification in Table 1-3. CON
FIGURE 1-1:
Timing Diagram. DS20002146D-page 6  2009-2014 Microchip Technology Inc. Document Outline 50 MHz, 200 µV Op Amps with mCal Features Typical Applications Design Aids Description Typical Application Circuit High Gain-Bandwidth Op Amp Portfolio Package Types 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings † 1.2 Specifications TABLE 1-1: DC Electrical Specifications TABLE 1-2: AC Electrical Specifications TABLE 1-3: Digital Electrical Specifications TABLE 1-4: Temperature Specifications 1.3 Timing Diagram FIGURE 1-1: Timing Diagram. 1.4 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Specifications. 2.0 Typical Performance Curves 2.1 DC Signal Inputs FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Voltage Repeatability (repeated calibration). FIGURE 2-4: Input Offset Voltage vs. Power Supply Voltage. FIGURE 2-5: Input Offset Voltage vs. Output Voltage. FIGURE 2-6: Low-Input Common Mode Voltage Headroom vs. Ambient Temperature. FIGURE 2-7: High-Input Common Mode Voltage Headroom vs. Ambient Temperature. FIGURE 2-8: Input Offset Voltage vs. Common Mode Voltage with VDD = 2.5V. FIGURE 2-9: Input Offset Voltage vs. Common Mode Voltage with VDD = 5.5V. FIGURE 2-10: CMRR and PSRR vs. Ambient Temperature. FIGURE 2-11: DC Open-Loop Gain vs. Ambient Temperature. FIGURE 2-12: Input Bias and Offset Currents vs. Ambient Temperature with VDD = +5.5V. FIGURE 2-13: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +85°C. FIGURE 2-14: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +125°C. FIGURE 2-15: Input Bias Current vs. Input Voltage (below VSS). 2.2 Other DC Voltages and Currents FIGURE 2-16: Ratio of Output Voltage Headroom to Output Current. FIGURE 2-17: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-18: Output Short-Circuit Current vs. Power Supply Voltage. FIGURE 2-19: Supply Current vs. Power Supply Voltage. FIGURE 2-20: Supply Current vs. Common Mode Input Voltage. FIGURE 2-21: Power-On Reset Voltages vs. Ambient Temperature. FIGURE 2-22: Normalized Internal Calibration Voltage. FIGURE 2-23: VCAL Input Resistance vs. Temperature. 2.3 Frequency Response FIGURE 2-24: CMRR and PSRR vs. Frequency. FIGURE 2-25: Open-Loop Gain vs. Frequency. FIGURE 2-26: Gain-Bandwidth Product and Phase Margin vs. Ambient Temperature. FIGURE 2-27: Gain-Bandwidth Product and Phase Margin vs. Common Mode Input Voltage. FIGURE 2-28: Gain-Bandwidth Product and Phase Margin vs. Output Voltage. FIGURE 2-29: Closed-Loop Output Impedance vs. Frequency. FIGURE 2-30: Gain Peaking vs. Normalized Capacitive Load. FIGURE 2-31: Channel-to-Channel Separation vs. Frequency. 2.4 Input Noise and Distortion FIGURE 2-32: Input Noise Voltage Density vs. Frequency. FIGURE 2-33: Input Noise Voltage Density vs. Input Common Mode Voltage with f = 100 Hz. FIGURE 2-34: Input Noise Voltage Density vs. Input Common Mode Voltage with f = 1 MHz. FIGURE 2-35: Input Noise plus Offset vs. Time with 0.1 Hz Filter. FIGURE 2-36: THD+N vs. Frequency. 2.5 Time Response FIGURE 2-37: Non-inverting Small Signal Step Response. FIGURE 2-38: Non-inverting Large Signal Step Response. FIGURE 2-39: Inverting Small Signal Step Response. FIGURE 2-40: Inverting Large Signal Step Response. FIGURE 2-41: The MCP651/1S/2/3/4/5/9 family shows no input phase reversal with overdrive. FIGURE 2-42: Slew Rate vs. Ambient Temperature. FIGURE 2-43: Maximum Output Voltage Swing vs. Frequency. 2.6 Calibration and Chip Select Response FIGURE 2-44: CAL/CS Current vs. Power Supply Voltage. FIGURE 2-45: CAL/CS Voltage, Output Voltage and Supply Current (for Side A) vs. Time with VDD = 2.5V. FIGURE 2-46: CAL/CS Voltage, Output Voltage and Supply Current (for Side A) vs. Time with VDD = 5.5V. FIGURE 2-47: CAL/CS Hysteresis vs. Ambient Temperature. FIGURE 2-48: CAL/CS Turn-On Time vs. Ambient Temperature. FIGURE 2-49: CAL/CS’s Pull-Down Resistor (RPD) vs. Ambient Temperature. FIGURE 2-50: Quiescent Current in Shutdown vs. Power Supply Voltage. FIGURE 2-51: Output Leakage Current vs. Output Voltage. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Calibration Common Mode Voltage Input 3.5 Calibrate/Chip Select Digital Input 3.6 Exposed Thermal Pad (EP) 4.0 Applications 4.1 Calibration and Chip Select FIGURE 4-1: Common-Mode Reference’s Input Circuitry. FIGURE 4-2: Setting VCM with External Resistors. 4.2 Input FIGURE 4-3: Simplified Analog Input ESD Structures. FIGURE 4-4: Protecting the Analog Inputs. FIGURE 4-5: Unity-Gain Voltage Limitations for Linear Operation. 4.3 Rail-to-Rail Output FIGURE 4-6: Output Current. FIGURE 4-7: Diagram for Resistive Load Power Calculations. FIGURE 4-8: Diagram for Capacitive Load Power Calculations. 4.4 Improving Stability FIGURE 4-9: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-10: Recommended RISO Values for Capacitive Loads. FIGURE 4-11: Amplifier with Parasitic Capacitance. FIGURE 4-12: Maximum Recommended RF vs. Gain. 4.5 Power Supply 4.6 High-Speed PCB Layout 4.7 Typical Applications FIGURE 4-13: Power Driver. FIGURE 4-14: Transimpedance Amplifier for an Optical Detector. FIGURE 4-15: H-Bridge Driver. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Microchip Advanced Part Selector (MAPS) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information 6.2 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service