Datasheet Summary SAM D21EL, SAM D21GL (Microchip) - 6
Manufacturer | Microchip |
Description | 32-bit ARM-Based Microcontrollers |
Pages / Page | 38 / 6 — 32-bit ARM-Based Microcontrollers. Configuration Summary. SAM D21G16L. … |
Revision | 02-01-2017 |
File Format / Size | PDF / 851 Kb |
Document Language | English |
32-bit ARM-Based Microcontrollers. Configuration Summary. SAM D21G16L. SAM D21ExL. Datasheet Summary
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32-bit ARM-Based Microcontrollers 2. Configuration Summary SAM D21G16L SAM D21ExL
Pins 48 32 General Purpose I/O-pins (GPIOs) 38 26 Flash 64KB 64/32KB SRAM 8KB 8/4KB Timer Counter (TC) instances 5 3 Waveform output channels per TC instance 2 2 Timer Counter for Control (TCC) instances 3 3 Waveform output channels per TCC 8/4/2 6/4/2 DMA channels 12 12 Serial Communication Interface (SERCOM) 6 4 instances Analog-to-Digital Converter (ADC) channels 18 14 Analog Comparators (AC) 4 4 Digital-to-Analog Converter (DAC) channels 1 1 Real-Time Counter (RTC) Yes Yes RTC alarms 1 1 RTC compare values One 32-bit value or One 32-bit value or two 16-bit values two 16-bit values External Interrupt lines 16 16 Maximum CPU frequency 48MHz Packages QFN QFN TQFP Oscillators 0.4-32MHz crystal oscillator (XOSC) 32.768kHz internal oscillator (OSC32K) 32KHz ultra-low-power internal oscillator (OSCULP32K) 8MHz high-accuracy internal oscillator (OSC8M) 48MHz Digital Frequency Locked Loop (DFLL48M) 96MHz Fractional Digital Phased Locked Loop (FDPLL96M) Event System channels 12 12 SW Debug Interface Yes Yes Watchdog Timer (WDT) Yes Yes © 2017 Microchip Technology Inc.
Datasheet Summary
40001885A-page 6 Document Outline Introduction Features Table of Contents 1. Description 2. Configuration Summary 3. Ordering Information 3.1. SAM D21ExL 3.2. SAM D21GxL 3.3. Device Identification 4. Block Diagram 5. Pinout 5.1. SAM D21GxL 5.1.1. QFN48 5.2. SAM D21ExL 5.2.1. QFN32 / TQFP32 6. Product Mapping 7. Processor And Architecture 7.1. Cortex M0+ Processor 7.1.1. Cortex M0+ Configuration 7.1.2. Cortex-M0+ Peripherals 7.1.3. Cortex-M0+ Address Map 7.1.4. I/O Interface 7.1.4.1. Overview 7.1.4.2. Description 7.2. Nested Vector Interrupt Controller 7.2.1. Overview 7.2.2. Interrupt Line Mapping 7.3. Micro Trace Buffer 7.3.1. Features 7.3.2. Overview 7.4. High-Speed Bus System 7.4.1. Features 7.4.2. Configuration 7.4.3. SRAM Quality of Service 7.5. AHB-APB Bridge 7.6. PAC - Peripheral Access Controller 7.6.1. Overview 7.6.2. Register Description 7.6.2.1. PAC0 Register Description 7.6.2.1.1. Write Protect Clear 7.6.2.1.2. Write Protect Set 7.6.2.2. PAC1 Register Description 7.6.2.2.1. Write Protect Clear 7.6.2.2.2. Write Protect Set 7.6.2.3. PAC2 Register Description 7.6.2.3.1. Write Protect Clear 7.6.2.3.2. Write Protect Set 8. Packaging Information 8.1. Thermal Considerations 8.1.1. Thermal Resistance Data 8.1.2. Junction Temperature 8.2. Package Drawings 8.2.1. 48 pin QFN 8.2.2. 32 pin TQFP 8.2.3. 32 pin QFN 8.3. Soldering Profile The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Certified by DNV Worldwide Sales and Service