Datasheet ATtiny212, ATTINY412 (Microchip) - 7

ATtiny212/412 3. Block Diagram Figure 3-1. ATtiny212 / ATtiny412 Block Diagram
UPDI / RESET
UPDI
CRC
CPU
OCD To detectors
Flash
M M M S
SRAM
S
BUS Matrix EEPROM
S S
NVMCTRL I N / O PORTS
PA[7:0] AINP0
U
AINN0
T AC0
OUT
D GPIOR A
OUT
E D T DAC0 V A A E T B CPUINT N A U B Detectors/
AIN[6, 7, 3:0]
ADC0 T S U references R S System O U Management RST POR
LUTn-IN[2:0]
CCL T
LUTn-OUT
I BOD/ Bandgap N RSTCTRL VLM G
WO[5:0]
TCA0 CLKCTRL N E T SLPCTRL
WO
TCB0 W O Clock generation R K
CLKOUT WO[A,B,C,D]
TCD0 OSC20M WDT
EXTCLK RXD
OSC32K
TXD
USART0
XCK TOSC1 XDIR
RTC XOSC32k
MISO TOSC2 MOSI
SPI0
SCK SS
EVSYS
EVOUT[n:0] SDA
TWI0
SCL © 2017 Microchip Technology Inc.
Datasheet Preliminary Summary
DS40001931A-page 7 Document Outline Introduction Features Table of Contents 1. tinyAVR® 1-Series Overview 1.1. Configuration Summary 1.1.1. Peripheral Summary 2. Ordering Information 2.1. ATtiny212 2.2. ATtiny412 3. Block Diagram 4. Pinout 4.1. 8-pin SOIC 5. I/O Multiplexing and Considerations 5.1. Multiplexed Signals 6. Package Drawings 6.1. 8-pin SOIC150 7. Thermal Considerations 7.1. Thermal Resistance Data 7.2. Junction Temperature The Microchip Web Site Customer Change Notification Service Customer Support Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Certified by DNV Worldwide Sales and Service