Datasheet MCP47FEBXX (Microchip) - 8

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MCP47FEBXX DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C  TA  +125°C (Extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V, Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF. Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters Sym. Min. Typ. Max. Units Conditions
Resistor Ladder RL 100 140 180 k 1.8V  VDD  5.5V, Resistance VREF  1.0V
(7 )
Resolution N 256 Taps 8-bit No Missing Codes (# of Resistors 1024 Taps 10-bit No Missing Codes and # of Taps) (see 4096 Taps 12-bit No Missing Codes
C.1 “Resolution”
) Nominal VOUT |VOUT - VOUTMEAN| — 0.5 1.0 % 2.7V  VDD  5.5V(
2 )
Match (
12
) /VOUTMEAN — — 1.2 % 1.8V(
2
) VOUT Tempco (see VOUT/T — 15 — ppm/°C Code = Mid-scale
C.19 “VOUT
(7Fh, 1FFh or 7FFh)
Temperature Coefficient”
) VREF pin Input VREF VSS — VDD V 1.8V  VDD  5.5V(
1 )
Voltage Range
Note 1
This parameter is ensured by design.
Note 2
This parameter is ensured by characterization.
Note 7
Resistance is defined as the resistance between the VREF pin (mode VRxB:VRxA = ‘10’) to VSS pin. For dual-channel devices (MCP47FEBX2), this is the effective resistance of the each resistor ladder. The resistance measurement is of the two resistor ladders measured in parallel.
Note 12
Variation of one output voltage to mean output voltage. DS20005375A-page 8  2015 Microchip Technology Inc. Document Outline 8-/10-/12-Bit Single/Dual Voltage Output Nonvolatile Digital-to-Analog Converters with I²C™ Interface Features Package Types General Description Applications MCP47FEBX1 Device Block Diagram (Single-Channel Output) MCP47FEBX2 Device Block Diagram (Dual-Channel Output) Device Features 1.0 Electrical Characteristics Absolute Maximum Ratings (†) DC Characteristics DC Notes: 1.1 Timing Waveforms and Requirements FIGURE 1-1: VOUT Settling Time Waveforms. TABLE 1-1: Wiper Settling Timing 1.2 I²C Mode Timing Waveforms and Requirements FIGURE 1-2: Power-on and Brown-out Reset Waveforms. FIGURE 1-3: I²C™ Power-Down Command Timing. TABLE 1-2: RESET Timing FIGURE 1-4: I²C™ Bus Start/Stop Bits Timing Waveforms. FIGURE 1-5: I²C™ Bus Start/Stop Bits Timing Waveforms. TABLE 1-3: I²C Bus Start/Stop Bits and LAT Requirements FIGURE 1-6: I²C™ Bus Timing Waveforms. TABLE 1-4: I²C Bus Requirements (Slave Mode) TABLE 1-5: I²C Bus Requirements (Slave Mode) Timing Table Notes: Temperature Specifications 2.0 Typical Performance Curves 3.0 Pin Descriptions TABLE 3-1: MCP47FEBX1 (Single-DAC) Pinout Description TABLE 3-2: MCP47FEBX2 (Dual-DAC) Pinout Description 3.1 Positive Power Supply Input (VDD) 3.2 Voltage Reference Pin (VREF) 3.3 Analog Output Voltage Pin (VOUT) 3.4 No Connect (NC) 3.5 Ground (VSS) 3.6 Latch Pin (LAT)/High-Voltage Command (HVC) 3.7 I²C - Serial Clock Pin (SCL) 3.8 I²C - Serial Data Pin (SDA) 4.0 General Description 4.1 Power-on Reset/Brown-out Reset (POR/BOR) FIGURE 4-1: Power-on Reset Operation. 4.2 Device Memory TABLE 4-1: Memory Map (x16) TABLE 4-2: Factory Default POR / BOR Values TABLE 4-3: SALCK Functional Description TABLE 4-4: WiperLock Technology Configuration Bits Functional Description Register 4-1: DAC0 and DAC1 Registers (Volatile and Nonvolatile) Register 4-2: Voltage Reference (VREF) Control Register (Volatile and Nonvolatile) (Addresses 08h and 18h) Register 4-3: Power-down Control Register (Volatile and Nonvolatile) (Addresses 09h, 19h) Register 4-4: Gain Control and System Status Register (Volatile) (Address 0Ah) Register 4-5: Gain Control and Slave Address Register (Nonvolatile) (Address 1AH) Register 4-6: DAC Wiperlock Technology Status Register (Volatile) (Address 0Bh) 5.0 DAC Circuitry FIGURE 5-1: MCP47FEBXX DAC Module Block Diagram. 5.1 Resistor Ladder FIGURE 5-2: Resistor Ladder Model Block Diagram. 5.2 Voltage Reference Selection FIGURE 5-3: Resistor Ladder Reference Voltage Selection Block Diagram. FIGURE 5-4: Reference Voltage Selection Implementation Block Diagram. 5.3 Output Buffer/VOUT Operation FIGURE 5-5: Output Driver Block Diagram. TABLE 5-1: Output Driver Gain TABLE 5-2: Theoretical Step Voltage (VS) (1) FIGURE 5-6: VOUT pin Slew Rate. FIGURE 5-7: Circuit to Stabilize Output Buffer for Large Capacitive Loads (CL). TABLE 5-3: DAC Input Code Vs. Calculated Analog Output (VOUT) (VDD = 5.0V) 5.4 Internal Band Gap TABLE 5-4: VOUT Using Band Gap 5.5 Latch Pin (LAT) FIGURE 5-8: LAT and DAC Interaction. FIGURE 5-9: Example use of LAT pin operation. 5.6 Power-Down Operation FIGURE 5-10: VOUT Power-Down Block Diagram. TABLE 5-5: Power-down bits and Output resistive load TABLE 5-6: DAC Current Sources 5.7 DAC Registers, Configuration Bits, and Status Bits 6.0 I²C Serial Interface Module FIGURE 6-1: Typical I2C Interface. 6.1 Overview 6.2 Interface Pins (SCL and SDA) 6.3 Communication Data Rates 6.4 POR/BOR 6.5 Device Memory Address 6.6 General Call Commands 6.7 Multi-Master Systems 6.8 Device I²C Slave Addressing FIGURE 6-2: Slave Address Bits in the I²C Control Byte. TABLE 6-1: I²C Address/Order Code 6.9 Entering High-Speed (HS) Mode FIGURE 6-3: HS Mode Sequence. 7.0 Device Commands TABLE 7-1: Device Commands - Number of Clocks 7.1 Write Command (Normal and High-Voltage) FIGURE 7-1: Write Random Address Command (Volatile and Nonvolatile Memory). FIGURE 7-2: I2C ACK / NACK Behavior (Write Command Example). FIGURE 7-3: Continuous Write Commands (Volatile Memory Only). 7.2 Read Command (Normal and High-Voltage) FIGURE 7-4: Read Command - Single Memory Address. FIGURE 7-5: Read Command - Last Memory Address Accessed. FIGURE 7-6: I2C ACK/NACK Behavior (Read Command Example). FIGURE 7-7: Continuous Read Command Of Specified Address. 7.3 General Call Commands FIGURE 7-8: General Call Formats. FIGURE 7-9: General Call Reset Command. FIGURE 7-10: General Call Wake-Up Command. 7.4 Modify Device Configuration Bit Commands 7.5 Enable Configuration Bit (High-Voltage) FIGURE 7-11: I2C Enable Command Sequence. 7.6 Disable Configuration Bit (High-Voltage) FIGURE 7-12: I2C Disable Command Sequence. FIGURE 7-13: Configuring All User Configuration Bits Command Sequence (MCP47FEBX1). FIGURE 7-14: Configuring All User Configuration Bits Command Sequence (MCP47FEBX2). 8.0 Typical Applications 8.1 Connecting to I²C BUS using Pull-Up Resistors FIGURE 8-1: I²C Bus Connection Test. 8.2 Power Supply Considerations FIGURE 8-2: Example Circuit. 8.3 Application Examples FIGURE 8-3: Example Circuit Of Set Point or Threshold Calibration. FIGURE 8-4: Single-Supply “Window” DAC. 8.4 Bipolar Operation FIGURE 8-5: Digitally-Controlled Bipolar Voltage Source Example Circuit. 8.5 Selectable Gain and Offset Bipolar Voltage Output FIGURE 8-6: Bipolar Voltage Source with Selectable Gain and Offset. 8.6 Designing a Double-Precision DAC FIGURE 8-7: Simple Double Precision DAC using MCP47FEBX2. 8.7 Building Programmable Current Source FIGURE 8-8: Digitally-Controlled Current Source. 8.8 Serial Interface Communication Times TABLE 8-1: Serial Interface Times / Frequencies 8.9 Software I²C Interface Reset Sequence FIGURE 8-9: Software Reset Sequence Format. 8.10 Design Considerations FIGURE 8-10: Typical Microcontroller Connections. TABLE 8-2: Package Footprint 9.0 Development Support 9.1 Development Tools 9.2 Technical Documentation TABLE 9-1: Development Tools TABLE 9-2: Technical Documentation FIGURE 9-1: MCP47FEBXX Evaluation Board Circuit Using TSSOP20EV. 10.0 Packaging Information 10.1 Package Marking Information Appendix A: Revision History Appendix B: I²C Serial Interface FIGURE B-1: Typical I²C Interface. B.1 Overview B.2 Signal Descriptions B.3 I²C Operation FIGURE B-2: Start Bit. FIGURE B-3: Data Bit. FIGURE B-4: Acknowledge Waveform. FIGURE B-5: Repeat Start Condition Waveform. FIGURE B-6: Stop Condition Receive or Transmit Mode. FIGURE B-7: Typical 8-Bit I²C Waveform Format. FIGURE B-8: I²C Data States and Bit Sequence. FIGURE B-9: I²C Slave Address Control Byte. FIGURE B-10: HS Mode Sequence. FIGURE B-11: General Call Formats. Appendix C: Terminology C.1 Resolution C.2 Least Significant Bit (LSb) C.3 Monotonic Operation FIGURE C-1: VW (VOUT). C.4 Full-Scale Error (EFS) C.5 Zero-Scale Error (EZS) C.6 Total Unadjusted Error (ET) C.7 Offset Error (EOS) FIGURE C-2: Offset Error (Zero Gain Error). C.8 Offset Error Drift (EOSD) C.9 Gain Error (EG) FIGURE C-3: Gain Error and Full-Scale Error Example. C.10 Gain-Error Drift (EGD) C.11 Integral Nonlinearity (INL) FIGURE C-4: INL Accuracy. C.12 Differential Nonlinearity (DNL) FIGURE C-5: DNL Accuracy. C.13 Settling Time C.14 Major-Code Transition Glitch C.15 Digital Feed-through C.16 -3 dB Bandwidth C.17 Power-Supply Sensitivity (PSS) C.18 Power-Supply Rejection Ratio (PSRR) C.19 VOUT Temperature Coefficient C.20 Absolute Temperature Coefficient C.21 Noise Spectral Density Product Identification System Trademarks Worldwide Sales and Service