Datasheet TC1321 (Microchip) - 7
| Manufacturer | Microchip |
| Description | 10-Bit Digital-to-Analog Converter with Two-Wire Interface |
| Pages / Page | 24 / 7 — TC1321. 3.0. DETAILED DESCRIPTION. 3.2. Output Amplifier. 3.3. Standby … |
| File Format / Size | PDF / 536 Kb |
| Document Language | English |
TC1321. 3.0. DETAILED DESCRIPTION. 3.2. Output Amplifier. 3.3. Standby Mode. TABLE 3-1:. STANDBY MODE OPERATION. SHDN Bit. Operating Mode
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TC1321 3.0 DETAILED DESCRIPTION 3.2 Output Amplifier
The TC1321 is a monolithic 10-bit digital-to-analog The TC1321 DAC output is buffered with an internal converter that is designed to operate from a single unity gain rail-to-rail input/output amplifier with a typical supply that can range from 2.7V to 5.5V. The DAC slew rate of 0.8V/µs. Maximum full scale transition consists of a data register (DATA), a configuration settling time is 10 µsec to within ±1/2LSB when loaded register (CONF), and a current output amplifier. The with 1 k in parallel with 100 pF. TC1321 uses an external reference which also determines the maximum output voltage.
3.3 Standby Mode
The TC1321 uses a current steering DAC based on an The TC1321 allows the host to put it into a Low Power array of matched current sources. This current, along (I with a precision resistor, converts the contents of the DD = 0.5 µA, typical y) Standby mode. DATA Register and V In this mode, the D/A conversion is halted. The SMBus REF into an output voltage, VOUT, that is given by: port operates normal y. Standby mode is enabled by setting the SHDN bit in the CONFIG register. Table 3-1 summarizes this operation. DATA V OUT = V -------- REF 1024
TABLE 3-1: STANDBY MODE OPERATION SHDN Bit Operating Mode 3.1 Reference Input
0 Normal The reference pin, VREF, is a buffered high-impedance input. Because of this, the load regulation of the 1 Standby reference source needs only to be able to tolerate leakage levels of current (less than 1 µA). VREF
3.4 SMBus Slave Address
accepts a voltage range from 0 to (VDD – 1.2V). Input capacitance is typically 10 pF. The TC1321 is internally programmed to have a default SMBus address value of 1001 000b. Seven other addresses are available by custom order (contact Microchip Worldwide Sales and Service). See Figure 3-1 for the location of address bits in SMBus protocol. 2010 Microchip Technology Inc. DS21387C-page 7 Document Outline TC1321 10-Bit Digital-to-Analog Converter with Two-Wire Interface 1.0 Electrical Characteristics 2.0 Pin Descriptions TABLE 2-1: Pin Function Table 2.1 External Voltage Reference Input (VREF) 2.2 Bi-Directional Serial Data Input and Output (SDA) 2.3 Serial Clock Input (SCL) 2.4 Supply Power Ground (VSS) 2.5 Output (VOUT) 2.6 No Connection (NC) 2.7 Output (DAC-OUT) 2.8 Positive Power Supply Input (VDD) 3.0 Detailed Description 3.1 Reference Input 3.2 Output Amplifier 3.3 Standby Mode TABLE 3-1: Standby Mode Operation 3.4 SMBus Slave Address FIGURE 3-1: SMBus/I2C Protocols. 4.0 Serial Port Operation TABLE 4-1: TC1321 Serial Bus Conventions 4.1 START Condition (START) 4.2 Address Byte 4.3 Acknowledge (ACK) 4.4 Data Byte 4.5 Stop Condition (STOP) FIGURE 4-1: SMBus/I2CTiming Diagrams. 4.6 Register Set and Programmer’s Model TABLE 4-2: TC1321 Command Set (READ_BYTE and WRITE_BYTE) TABLE 4-3: Configuration Register (CONFIG), 8-Bit, Read/Write TABLE 4-4: Data Register (DATA), 10-Bit, Read/Write 4.7 Register Set Summary TABLE 4-5: TC1321 Register Set Summary 5.0 Packaging Information 5.1 Package Marking Information Appendix A: Revision History Product Identification System Worldwide Sales and Service
TC1321 3.0 DETAILED DESCRIPTION 3.2 Output Amplifier
The TC1321 is a monolithic 10-bit digital-to-analog The TC1321 DAC output is buffered with an internal converter that is designed to operate from a single unity gain rail-to-rail input/output amplifier with a typical supply that can range from 2.7V to 5.5V. The DAC slew rate of 0.8V/µs. Maximum full scale transition consists of a data register (DATA), a configuration settling time is 10 µsec to within ±1/2LSB when loaded register (CONF), and a current output amplifier. The with 1 k in parallel with 100 pF. TC1321 uses an external reference which also determines the maximum output voltage.
3.3 Standby Mode
The TC1321 uses a current steering DAC based on an The TC1321 allows the host to put it into a Low Power array of matched current sources. This current, along (I with a precision resistor, converts the contents of the DD = 0.5 µA, typical y) Standby mode. DATA Register and V In this mode, the D/A conversion is halted. The SMBus REF into an output voltage, VOUT, that is given by: port operates normal y. Standby mode is enabled by setting the SHDN bit in the CONFIG register. Table 3-1 summarizes this operation. DATA V OUT = V -------- REF 1024
TABLE 3-1: STANDBY MODE OPERATION SHDN Bit Operating Mode 3.1 Reference Input
0 Normal The reference pin, VREF, is a buffered high-impedance input. Because of this, the load regulation of the 1 Standby reference source needs only to be able to tolerate leakage levels of current (less than 1 µA). VREF
3.4 SMBus Slave Address
accepts a voltage range from 0 to (VDD – 1.2V). Input capacitance is typically 10 pF. The TC1321 is internally programmed to have a default SMBus address value of 1001 000b. Seven other addresses are available by custom order (contact Microchip Worldwide Sales and Service). See Figure 3-1 for the location of address bits in SMBus protocol. 2010 Microchip Technology Inc. DS21387C-page 7 Document Outline TC1321 10-Bit Digital-to-Analog Converter with Two-Wire Interface 1.0 Electrical Characteristics 2.0 Pin Descriptions TABLE 2-1: Pin Function Table 2.1 External Voltage Reference Input (VREF) 2.2 Bi-Directional Serial Data Input and Output (SDA) 2.3 Serial Clock Input (SCL) 2.4 Supply Power Ground (VSS) 2.5 Output (VOUT) 2.6 No Connection (NC) 2.7 Output (DAC-OUT) 2.8 Positive Power Supply Input (VDD) 3.0 Detailed Description 3.1 Reference Input 3.2 Output Amplifier 3.3 Standby Mode TABLE 3-1: Standby Mode Operation 3.4 SMBus Slave Address FIGURE 3-1: SMBus/I2C Protocols. 4.0 Serial Port Operation TABLE 4-1: TC1321 Serial Bus Conventions 4.1 START Condition (START) 4.2 Address Byte 4.3 Acknowledge (ACK) 4.4 Data Byte 4.5 Stop Condition (STOP) FIGURE 4-1: SMBus/I2CTiming Diagrams. 4.6 Register Set and Programmer’s Model TABLE 4-2: TC1321 Command Set (READ_BYTE and WRITE_BYTE) TABLE 4-3: Configuration Register (CONFIG), 8-Bit, Read/Write TABLE 4-4: Data Register (DATA), 10-Bit, Read/Write 4.7 Register Set Summary TABLE 4-5: TC1321 Register Set Summary 5.0 Packaging Information 5.1 Package Marking Information Appendix A: Revision History Product Identification System Worldwide Sales and Service
