Datasheet MCP4725 (Microchip) - 4

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MCP4725 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications:
Unless otherwise indicated, all parameters apply at VDD = + 2.7V to 5.5V, VSS = 0V, RL = 5 kΩ from VOUT to VSS, CL = 100 pF, TA = -40°C to +125°C. Typical values are at +25°C.
Parameter Sym Min Typ Max Units Conditions
Power Up Time TPU — 2.5 — µs VDD = 5V — 5 — µs VDD = 3V Exit Power-down Mode, (Started from falling edge of ACK pulse) DC Output Impedance ROU T — 1 — Ω Normal mode (VOUT to VSS) — 1 — kΩ Power-Down Mode 1 (VOUT to VSS) — 100 — kΩ Power-Down Mode 2 (VOUT to VSS) — 500 — kΩ Power-Down Mode 3 (VOUT to VSS) Supply Voltage Power-up VDD_RAMP 1 — — V/ms Validation only. Ramp Rate for EEPROM loading
Dynamic Performance
Major Code Transition — 45 — nV-s 1 LSB change around major Glitch carry (from 800h to 7FFh) (
Note 2)
Digital Feedthrough — <10 — nV-s
Note 2 Digital Interface
Output Low Voltage VOL — — 0.4 V IOL = 3 mA Input High Voltage VIH 0.7VDD — — V (SDA and SCL Pins) Input Low Voltage VIL — — 0.3VDD V (SDA and SCL Pins) Input High Voltage VA0-Hi 0.8VDD — —
Note 4
(A0 Pin) Input Low Voltage VA0-IL — — 0.2VDD
Note 4
(A0 Pin) Input Leakage ILI — — ±1 µA SCL = SDA = A0 = VSS or SCL = SDA = A0 = VDD Pin Capacitance CPIN — — 3 pF
Note 2 EEPROM
EEPROM Write Time TWRITE — 25 50 ms Data Retention — 200 — Years At +25°C,
(Note 2 )
Endurance 1 — — Million At +25°C,
(Note 2 )
Cycles
Note 1:
Test Code Range: 100 to 4000.
2:
This parameter is ensure by design and not 100% tested.
3:
Within 1/2 LSB of the final value when code changes from 1/4 to 3/4 (400h to C00h) of full scale range.
4:
Logic state of external address selection pin (A0 pin). DS22039D-page 4 © 2009 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics 2.0 Typical Performance Curves FIGURE 2-1: DNL vs. Code (VDD = 5.5V). FIGURE 2-2: DNL vs. Code and Temperature (TA = -40°C to +125°C). FIGURE 2-3: DNL vs. Code (VDD = 2.7V). FIGURE 2-4: DNL vs. Code and Temperature (TA = -40°C to +125°C). FIGURE 2-5: INL vs. Code. FIGURE 2-6: INL vs. Code and Temperature (VDD = 5.5V). FIGURE 2-7: INL vs. Code and Temperature (VDD = 2.7V). FIGURE 2-8: Zero Scale Error vs. Temperature (Code = 000d). FIGURE 2-9: Full Scale Error vs. Temperature (Code = 4095d). FIGURE 2-10: Output Error vs. Temperature (Code = 4000d). FIGURE 2-11: IDD vs. Temperature. FIGURE 2-12: IDD Histogram . FIGURE 2-13: IDD Histogram. FIGURE 2-14: Offset Error vs. Temperature and VDD. FIGURE 2-15: VOUT vs. Resistive Load. FIGURE 2-16: Source and Sink Current Capability. FIGURE 2-17: VIN High Threshold vs. Temperature and VDD. FIGURE 2-18: VIN Low Threshold vs. Temperature and VDD. FIGURE 2-19: Full Scale Settling Time. FIGURE 2-20: Full Scale Settling Time. FIGURE 2-21: Half Scale Settling Time. FIGURE 2-22: Half Scale Settling Time. FIGURE 2-23: Code Change Glitch. FIGURE 2-24: Exiting Power Down Mode. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Output Voltage (VOUT) 3.2 Supply Voltage (VDD or VSS) 3.3 Serial Data Pin (SDA) 3.4 Serial Clock Pin (SCL) 3.5 Device Address Selection Pin (A0) 4.0 Terminology 4.1 Resolution 4.2 LSB 4.3 Integral Nonlinearity (INL) or Relative Accuracy FIGURE 4-1: INL Accuracy. 4.4 Differential Nonlinearity (DNL) FIGURE 4-2: DNL Accuracy. 4.5 Offset Error FIGURE 4-3: Offset Error. 4.6 Gain Error 4.7 Full Scale Error (FSE) FIGURE 4-4: Gain Error and Full Scale Error. 4.8 Gain Error Drift 4.9 Offset Error Drift 4.10 Settling Time 4.11 Major-Code Transition Glitch 4.12 Digital Feedthrough 5.0 General Description 5.1 Output Voltage 5.2 LSB SIZE TABLE 5-1: LSB SIZES for MCP4725 (example) 5.3 Voltage Reference 5.4 Reset Conditions 5.5 Normal and Power-Down Modes TABLE 5-2: Power-down bits FIGURE 5-1: Output Stage for Power- Down Mode. 5.6 Non-Volatile EEPROM Memory TABLE 5-3: EEPROM Memory and Factory Default Settings (Total number of bits: 14 bits) TABLE 5-4: DAC register 6.0 Theory Of Operation 6.1 Write Commands TABLE 6-1: Input Data Coding TABLE 6-2: Write Command Type FIGURE 6-1: Fast Mode Write Command. FIGURE 6-2: Write Commands for DAC Input Register and EEPROM. 6.2 read command FIGURE 6-3: Read Command and Output Data Format. 7.0 I2C Serial Interface Communication 7.1 OVERVIEW 7.2 Device Addressing FIGURE 7-1: Device Addressing. 7.3 General Call FIGURE 7-2: General Call Address Format. 7.4 High-Speed (HS) Mode 7.5 I2C BUS CHARACTERISTICS FIGURE 7-3: Data Transfer Sequence On The Serial Bus. TABLE 7-1: I2c serial timing Specifications FIGURE 7-4: I2C Bus Timing Data. 8.0 Typical Applications 8.1 Connecting to I2C BUS using Pull-Up Resistors FIGURE 8-1: I2C Bus Interface Connection with A0 pin tied to VSS. FIGURE 8-2: I2C Bus Connection Test. 8.2 Using Non-Volatile EEPROM Memory 8.3 Power Supply Considerations 8.4 Layout Considerations 8.5 Application Examples FIGURE 8-3: Digitally Controllable Current Source. 9.0 Development Support 9.1 Evaluation & Demonstration Boards FIGURE 9-1: MCP4725 SOT-23-6 Evaluation Board. FIGURE 9-2: Setup for the MCP4725 SOT-23-6 Evaluation Board with PICkit™ Serial Analyzer. FIGURE 9-3: Example of PICkit™ Serial User Interface. 10.0 Packaging Information 10.1 Package Marking Information Corporate Office Atlanta Boston Chicago Cleveland Fax: 216-447-0643 Dallas Detroit Kokomo Toronto Fax: 852-2401-3431 Australia - Sydney China - Beijing China - Shanghai India - Bangalore Korea - Daegu Korea - Seoul Singapore Taiwan - Taipei Fax: 43-7242-2244-393 Denmark - Copenhagen France - Paris Germany - Munich Italy - Milan Spain - Madrid UK - Wokingham Worldwide Sales and Service