Datasheet LTC4300A-3 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | Level Shifting Hot Swappable 2-Wire Bus Buffer with Enable |
| Pages / Page | 14 / 1 — FeaTures. DescripTion. Bidirectional Buffer* for SDA and SCL Lines. … |
| File Format / Size | PDF / 216 Kb |
| Document Language | English |
FeaTures. DescripTion. Bidirectional Buffer* for SDA and SCL Lines. Increases Fanout
Model Line for this Datasheet
- LTC4300A-3CDD#PBF LTC4300A-3CDD#PBF LTC4300A-3CDD#TRPBF LTC4300A-3CDD#TRPBF LTC4300A-3CMS8#PBF LTC4300A-3CMS8#PBF LTC4300A-3CMS8#TRPBF LTC4300A-3CMS8#TRPBF LTC4300A-3IDD#PBF LTC4300A-3IDD#PBF LTC4300A-3IDD#TRPBF LTC4300A-3IDD#TRPBF LTC4300A-3IMS8#PBF LTC4300A-3IMS8#PBF LTC4300A-3IMS8#TRPBF LTC4300A-3IMS8#TRPBF
Text Version of Document
LTC4300A-3 Level-Shifting Hot Swappable 2-Wire Bus Buffer with Enable
FeaTures DescripTion
n
Bidirectional Buffer* for SDA and SCL Lines
The LTC®4300A-3 hot swappable 2-wire bus buffer allows
Increases Fanout
I/O card insertion into a live backplane without corruption n
Prevents SDA and SCL Corruption During Live
of the data and clock busses. When the connection is made,
Board Insertion and Removal From Backplane
the LTC4300A-3 provides bidirectional buffering, keeping n
Logic Threshold ENABLE Input
the backplane and card capacitances isolated. Rise time n Isolates Input SDA and SCL Lines From Output accelerator circuitry allows the use of weaker DC pull-up n Compatible with I2C, I2C Fast Mode and SMBus currents while still meeting rise time requirements. During Standards (Up to 400kHz Operation) insertion, the SDA and SCL lines are precharged to 1V to n 1V Precharge on all SDA and SCL Lines minimize bus disturbances. n Supports Clock Stretching, Arbitration and The LTC4300A-3 provides level translation between Synchronization 3.3V and 5V supplies. The backplane and card can both ■ 5V to 3.3V Level Translation be powered with supplies ranging from 2.7V to 5.5V. ■ High Impedance SDA, SCL Pins for VCC = 0V, The LTC4300A-3 also incorporates a CMOS threshold VCC2 = 0V ENABLE pin which forces the part into a low current mode ■ Small 8-Lead DFN and MSOP Packages and isolates the card from the backplane. When driven to V
applicaTions
CC, the ENABLE pin sets normal operation. n The LTC4300A-3 is available in the MSOP and 3mm × 3mm Hot Board Insertion n DFN packages. Servers L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and n Capacitance Buffer/Bus Extender Hot Swap and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks n Desktop Computer are the property of their respective owners. *Patent pending.
Typical applicaTion
VCC V
Input–Output Connection
3.3V CC2 0.01µF 0.01µF 10k 10k 8 1 10k 10k INPUT 3 2 OUTPUT SIDE SCLIN SCLOUT SIDE 50pF 150pF 0.5V/DIV 6 7 SDAIN SDAOUT 4300a3 TA01b 200ns/DIV 5 LTC4300A-3 OFF ON ENABLE GND 4300a3 TA01 4 4300a3fa 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Related Parts Typical Application
FeaTures DescripTion
n
Bidirectional Buffer* for SDA and SCL Lines
The LTC®4300A-3 hot swappable 2-wire bus buffer allows
Increases Fanout
I/O card insertion into a live backplane without corruption n
Prevents SDA and SCL Corruption During Live
of the data and clock busses. When the connection is made,
Board Insertion and Removal From Backplane
the LTC4300A-3 provides bidirectional buffering, keeping n
Logic Threshold ENABLE Input
the backplane and card capacitances isolated. Rise time n Isolates Input SDA and SCL Lines From Output accelerator circuitry allows the use of weaker DC pull-up n Compatible with I2C, I2C Fast Mode and SMBus currents while still meeting rise time requirements. During Standards (Up to 400kHz Operation) insertion, the SDA and SCL lines are precharged to 1V to n 1V Precharge on all SDA and SCL Lines minimize bus disturbances. n Supports Clock Stretching, Arbitration and The LTC4300A-3 provides level translation between Synchronization 3.3V and 5V supplies. The backplane and card can both ■ 5V to 3.3V Level Translation be powered with supplies ranging from 2.7V to 5.5V. ■ High Impedance SDA, SCL Pins for VCC = 0V, The LTC4300A-3 also incorporates a CMOS threshold VCC2 = 0V ENABLE pin which forces the part into a low current mode ■ Small 8-Lead DFN and MSOP Packages and isolates the card from the backplane. When driven to V
applicaTions
CC, the ENABLE pin sets normal operation. n The LTC4300A-3 is available in the MSOP and 3mm × 3mm Hot Board Insertion n DFN packages. Servers L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and n Capacitance Buffer/Bus Extender Hot Swap and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks n Desktop Computer are the property of their respective owners. *Patent pending.
Typical applicaTion
VCC V
Input–Output Connection
3.3V CC2 0.01µF 0.01µF 10k 10k 8 1 10k 10k INPUT 3 2 OUTPUT SIDE SCLIN SCLOUT SIDE 50pF 150pF 0.5V/DIV 6 7 SDAIN SDAOUT 4300a3 TA01b 200ns/DIV 5 LTC4300A-3 OFF ON ENABLE GND 4300a3 TA01 4 4300a3fa 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Revision History Related Parts Typical Application
