Datasheet LTC4307 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Low Offset Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery |
| Pages / Page | 16 / 9 — OPERATION. Figure 2. Input-Output Rising Edge Waveforms. Figure 3. … |
| File Format / Size | PDF / 181 Kb |
| Document Language | English |
OPERATION. Figure 2. Input-Output Rising Edge Waveforms. Figure 3. Input-Output Falling Edge Waveforms. Bus Stuck Low Timeout
Model Line for this Datasheet
- LTC4307CDD#PBF LTC4307CDD#PBF LTC4307CDD#TRPBF LTC4307CDD#TRPBF LTC4307CMS8#PBF LTC4307CMS8#PBF LTC4307CMS8#TRPBF LTC4307CMS8#TRPBF LTC4307IDD#PBF LTC4307IDD#PBF LTC4307IDD#TRPBF LTC4307IDD#TRPBF LTC4307IMS8#3ZZPBF LTC4307IMS8#3ZZTRPBF LTC4307IMS8#PBF LTC4307IMS8#PBF LTC4307IMS8#TRPBF LTC4307IMS8#TRPBF
Text Version of Document
LTC4307
OPERATION
OUTPUT SIDE INPUT SIDE INPUT SIDE OUTPUT SIDE 50pF 150pF 150pF 50pF 1V/DIV 1V/DIV 1V/DIV 1V/DIV 200ns/DIV 4307 F02 200ns/DIV 4307 F03
Figure 2. Input-Output Rising Edge Waveforms Figure 3. Input-Output Falling Edge Waveforms Bus Stuck Low Timeout
low. When the pin is driven above 2V, the part waits for When SDAOUT or SCLOUT is low, an internal timer is data transactions on both the backplane and card sides to started. The timer is only reset by that respective input be complete (as described in the Start-Up section) before going high. If it does not go high within 30ms (typical) connecting the two sides. At this time the internal pull- the connection between SDAIN and SDAOUT, and between down on READY releases. When ENABLE is low, automatic SCLIN and SCLOUT is broken. After at least 40μs, the clocking is disabled. LTC4307 automatically generates up to 16 clock pulses A rising edge on ENABLE after a bus stuck low condition at 8.5kHz (typical) on SCLOUT in an attempt to unstick has occurred forces a connection between SDAIN, SDAOUT, the bus. When the clock pulses are completed, a stop bit and SCLIN, SCLOUT even if the bus stuck low condition will be generated on SCLOUT and SDAOUT to reset any has not been cleared. At this time the 30ms timer is reset circuity on that bus. When the low SDAOUT or SCLOUT but not disabled. pin goes high, a connection is enabled waiting for a stop bit or a bus idle to make a connection.
Rise Time Accelerators
When powering up into a bus stuck low condition, the Once connection has been established, rise time accelerator connection circuitry joining the SDA and SCL busses on circuits on all four SDA and SCL pins are enabled. During the I/O card with those on the backplane is not activated positive bus transitions, the rise time accelerators provide and is only reset when SDAOUT and SCLOUT are high. strong, slew-limited pull-up currents that make the bus 30ms after UVLO, automatic clocking takes place as voltage rise at a rate of 100V/μs. The rise time accelerators described above. signifi cantly improve system reliability in two ways. First, they provide smooth, controlled transitions during rising
READY Digital Output
edges for both small and large systems. Because the ac- This pin provides a digital fl ag which is low when either celerator pull-up impedance is signifi cantly lower than the ENABLE is low, the start-up sequence described earlier in bus pull-up resistance, the system is much less susceptible this section has not been completed, or the LTC4307 has to noise on rising edges. Second, the accelerators allow disconnected due to a stuck bus condition. READY goes users to choose large bus pull-up resistors, reducing power high when ENABLE is high and the backplane and card consumption and improving logic low noise margin. sides are connected. The pin is driven by an open-drain For these reasons, it is strongly recommended that users pull-down capable of sinking 3mA while holding 0.4V on choose bus pull-up resistors so that the bus will rise on its the pin. Connect a resistor to VCC to provide the pull-up. own at a rate of at least 0.8V/μs to guarantee activation of the accelerators. The rise time accelerators are disabled
ENABLE
until the sequence of events described in the start-up sec- When the ENABLE pin is driven below 0.8V with respect to tion has been completed. They are also disabled during the LTC4307’s ground, the backplane side is disconnected automatic clocking. from the card side and the READY pin is internally pulled 4307f 9
OPERATION
OUTPUT SIDE INPUT SIDE INPUT SIDE OUTPUT SIDE 50pF 150pF 150pF 50pF 1V/DIV 1V/DIV 1V/DIV 1V/DIV 200ns/DIV 4307 F02 200ns/DIV 4307 F03
Figure 2. Input-Output Rising Edge Waveforms Figure 3. Input-Output Falling Edge Waveforms Bus Stuck Low Timeout
low. When the pin is driven above 2V, the part waits for When SDAOUT or SCLOUT is low, an internal timer is data transactions on both the backplane and card sides to started. The timer is only reset by that respective input be complete (as described in the Start-Up section) before going high. If it does not go high within 30ms (typical) connecting the two sides. At this time the internal pull- the connection between SDAIN and SDAOUT, and between down on READY releases. When ENABLE is low, automatic SCLIN and SCLOUT is broken. After at least 40μs, the clocking is disabled. LTC4307 automatically generates up to 16 clock pulses A rising edge on ENABLE after a bus stuck low condition at 8.5kHz (typical) on SCLOUT in an attempt to unstick has occurred forces a connection between SDAIN, SDAOUT, the bus. When the clock pulses are completed, a stop bit and SCLIN, SCLOUT even if the bus stuck low condition will be generated on SCLOUT and SDAOUT to reset any has not been cleared. At this time the 30ms timer is reset circuity on that bus. When the low SDAOUT or SCLOUT but not disabled. pin goes high, a connection is enabled waiting for a stop bit or a bus idle to make a connection.
Rise Time Accelerators
When powering up into a bus stuck low condition, the Once connection has been established, rise time accelerator connection circuitry joining the SDA and SCL busses on circuits on all four SDA and SCL pins are enabled. During the I/O card with those on the backplane is not activated positive bus transitions, the rise time accelerators provide and is only reset when SDAOUT and SCLOUT are high. strong, slew-limited pull-up currents that make the bus 30ms after UVLO, automatic clocking takes place as voltage rise at a rate of 100V/μs. The rise time accelerators described above. signifi cantly improve system reliability in two ways. First, they provide smooth, controlled transitions during rising
READY Digital Output
edges for both small and large systems. Because the ac- This pin provides a digital fl ag which is low when either celerator pull-up impedance is signifi cantly lower than the ENABLE is low, the start-up sequence described earlier in bus pull-up resistance, the system is much less susceptible this section has not been completed, or the LTC4307 has to noise on rising edges. Second, the accelerators allow disconnected due to a stuck bus condition. READY goes users to choose large bus pull-up resistors, reducing power high when ENABLE is high and the backplane and card consumption and improving logic low noise margin. sides are connected. The pin is driven by an open-drain For these reasons, it is strongly recommended that users pull-down capable of sinking 3mA while holding 0.4V on choose bus pull-up resistors so that the bus will rise on its the pin. Connect a resistor to VCC to provide the pull-up. own at a rate of at least 0.8V/μs to guarantee activation of the accelerators. The rise time accelerators are disabled
ENABLE
until the sequence of events described in the start-up sec- When the ENABLE pin is driven below 0.8V with respect to tion has been completed. They are also disabled during the LTC4307’s ground, the backplane side is disconnected automatic clocking. from the card side and the READY pin is internally pulled 4307f 9
