Datasheet LTC4308 (Analog Devices) - 8

LTC4308
OPERATION Start-Up
0.3 • VCC, while the SCLIN and SDAIN busses are tolerant When the LTC4308 fi rst receives power on its V of bus logic low voltages up to 0.6V. A high occurs when CC pin, either during power-up or live insertion, it starts in an all devices on the input and output pins release high. under voltage lockout (UVLO) state, ignoring any activity When the LTC4308 senses a rising edge on either of the on the SDA or SCL pins until VCC rises above 2V (typical). output busses, with a slew rate greater than 0.8V/μs, the This ensures the LTC4308 does not try to function until internal pull-down device for the respective bus is deacti- enough supply voltage is present. vated at bus voltages as low as 0.48V. This methodology During this time, the 1V precharge circuitry is actively maximizes the effectiveness of the rise time accelerator forcing 1V through 100k nominal resistors to the SDAOUT circuitry and maintains compatibility with other devices and SCLOUT pins. Because SDAOUT and SCLOUT pins in the LTC4300 bus buffer family. Care must be taken to may be plugged into a live backplane, where the voltage ensure devices participating in clock stretching or arbitra- on the backplane SDA and SCL busses can be anywhere tion is capable of forcing logic low voltages below 0.48V between 0V and V at the LTC4308’s SCLOUT and SDAOUT pins. CC, precharging SCLOUT and SDAOUT to 1V minimizes the worst-case voltage differential these These important features ensure the I2C specifi cation pins will see at the moment of contact, therefore minimizing protocols such as clock stretching, clock synchroniza- the amount of disturbance caused by the I/O card. tion, arbitration, and acknowledge function seamlessly Once the LTC4308 exits from UVLO, it monitors both the in all cases as specifi ed, regardless of how the devices in input and output pins for either a stop bit or a bus idle the system are connected to the LTC4308. condition to indicate the completion of data transactions. Another key feature provided by the connection circuitry When both sides are idle or one side has a stop bit while the is input and output bus capacitance isolation through other is idle, the connection circuitry is activated, joining bidirectional buffering. Because of this isolation, the the SDA and SCL pins on the input bus with those on the waveforms on the input busses look slightly different than output bus. Because SDAIN and SCLIN are monitored for the corresponding output bus waveforms, as described a stop bit or bus idle as a condition for connection, they in the next two sections. may also be used for Hot-Swapping, but note that these pins are not precharged.
Offset Voltages
When a logic low is driven on SDAIN or SCLIN, the LTC4308
Connection Circuitry
regulates SDAOUT or SCLOUT, respectively, to a higher Once the connection circuitry is activated, the functionality voltage, typically 300mV above the driven low voltage. of the input and output bus of the respective SDA or SCL When a logic low is driven on SCLOUT or SDAOUT, the pins is identical. A low forced on either output or input pin LTC4308 regulates SCLIN or SDAIN, respectively, to a volt- at any time results in both pin voltages forced low. The age that is typically 200mV below the driven low voltage. LTC4308 SCLOUT and SDAOUT busses are tolerant of I2C These offsets are nearly independent of pull-up current bus DC logic low voltages up to the VIL specifi cation of (see Typical Performance Characteristics). 4308f 8