Datasheet LTC4314 (Analog Devices) - 8

LTC4314
OPERATION
The Block Diagram shows the major functional blocks of The LTC4314 is designed to sink a minimum total bus the LTC4314. The LTC4314 is a 1:4 multiplexer with ca- current IOL of 4mA while holding a VOL of 0.4V. If multiple pacitance buffering for I2C signals. Capacitance buffering output channels are enabled, the bus current of all enabled is achieved by use of back to back buffers on the clock channels needs to be summed to get the total bus current. and data channels which isolate the SDAIN and SCLIN See the Typical Performance Characteristics curves for IOL capacitances from the SDAOUT and SCLOUT capacitances as a function of temperature. respectively. All SDA and SCL pins are fully bidirectional. A high occurs when all devices on the input and output The high noise margin allows the LTC4314 to operate sides release high. Once the bus voltages rise above the with I2C devices that drive a non-compliant high VOL. V Multiplexing is done using N-channel MOSFETs that are IL, RISING level, which is determined by the state of the ACC pin, the buffers are turned off. The rise time accelerators controlled by dedicated ENABLE pins. When enabled, are turned on at a slightly higher voltage. The rise time rise time accelerator pull-up currents IRTA turn on dur- accelerators accelerate the rising edges of the SDA,SCL ing rising edges to reduce system rise time. In a typical inputs and selected outputs up to voltages of 0.9•V application the input side bus is pulled up to V CC and CC and the 0.8•V output side busses are pulled up to V CC2 respectively, provided that the busses on their CC2 although these own are rising at a minimum rate of 0.2V/μs as determined are not requirements. VCC is the primary power supply to by the slew rate detectors. ACC is a 3-state input that con- the LTC4314. VCC and VCC2 serve as the input and output trols V side rise time accelerator supplies respectively. Ground- IL,RISING, the rise time accelerator turn-on voltage and the rise time accelerator pull-up strength. ing VCC2 disables the output side rise time accelerators. The multiplexer N-channel MOSFET gates of the enabled The LTC4314 detects a bus stuck low (fault) condition channels are driven to V when both clock and data busses are not simultaneously CC2 if VCC2 is > 1.8V, otherwise they are driven to V high at least once in 45ms. The voltage monitoring for a CC. stuck low condition is done on the common internal node When the LTC4314 fi rst receives power on its VCC pin, it of the clock and data outputs. Hence a stuck low condition starts out in an undervoltage lockout mode (UVLO) until is detected only if it occurs on an enabled output channel. 110μs after VCC exceeds 2.3V. During this time, the buffers When a stuck bus occurs, the LTC4314 asserts the FAULT and rise time accelerators are disabled, the multiplexer fl ag. If DISCEN is tied high, the LTC4314 also disconnects gates are off and the LTC4314 ignores transitions on the the input and output sides. After waiting at least 40μs, it clock and data pins independent of the state of the ENABLE generates up to sixteen 5.5kHz clock pulses on the enabled pins. VCC2 transitions from a high to a low or vice-versa SCLOUT pins and a stop bit to attempt to free the stuck across a 1.8V threshold also cause the LTC4314 to dis- bus. If the bus recovers high before 16 clocks are issued, able the buffers, rise time accelerators and transmission the LTC4314 ceases issuing clocks and generates a stop gates and to ignore the clock and data pins until 110μs bit. If DISCEN is tied low, a stuck bus event only causes after that transition. Assuming that the LTC4314 is not FAULT fl ag assertion. Disconnection of the input and output in UVLO mode, when one or more ENABLEs is asserted, sides and clock generation do not occur. Once the stuck the LTC4314 activates the connection circuitry between bus recovers and the fault has been cleared, in order for a the SDAIN, SCLIN inputs and selected output channels. connection to be established between the input and output The input rise time accelerators and the output rise time sides, all ENABLE pins need to be driven low followed accelerators of the selected channels are also enabled at by the assertion high of the desired ENABLE pins. When this time. When a SDA,SCL input pin or output pin on an powering into a stuck low condition, the LTC4314 upon enabled output channel is driven below the VIL,FALLING exiting UVLO will connect the input and output sides for level of 0.33•VMIN, the buffers are turned on and the logic 45ms until a stuck bus timeout event is detected. low level is propagated though the LTC4314 to the other side. For VCC2 > 1.8V, VMIN is the lower of the VCC and VCC2 voltages. For VCC2 < 1.8V, VMIN is the VCC voltage. 4314f 8