Datasheet LTC5507 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | 100kHz to 1GHz RF Power Detector |
| Pages / Page | 8 / 4 — PI FU CTIO S. SHDN (Pin 1):. VCC (Pin 4):. PCAP (Pin 5):. GND (Pin 2):. … |
| File Format / Size | PDF / 134 Kb |
| Document Language | English |
PI FU CTIO S. SHDN (Pin 1):. VCC (Pin 4):. PCAP (Pin 5):. GND (Pin 2):. RFIN (Pin 6):. VOUT (Pin 3):. BLOCK DIAGRA. Figure 2
Model Line for this Datasheet
Text Version of Document
LTC5507
U U U PI FU CTIO S SHDN (Pin 1):
Shutdown Input. A logic low or no-connect
VCC (Pin 4):
Power Supply Voltage, 2.7V to 6V. VCC should on the SHDN pin places the part in shutdown mode. A logic be bypassed with 0.1µF and 100pF ceramic capacitors. high enables the part. SHDN has an internal 150k pull
PCAP (Pin 5):
Peak Detector Hold Capacitor. Capacitor down resistor to ensure that the part is in shutdown when value is dependent on RF frequency. Capacitor must be the enable driver is in a tri-state condition. connected between PCAP and VCC.
GND (Pin 2):
System Ground.
RFIN (Pin 6):
RF Input Voltage. Referenced to VCC. A
VOUT (Pin 3):
Buffered and Level Shifted Detector Output coupling capacitor must be used to connect to the RF Voltage. signal source. This pin has an internal 250Ω termination and an internal Schottky diode detector.
W BLOCK DIAGRA
VCC 4 GAIN + COMPRESSION BUFFER 3 VOUT C1 250Ω RF – SOURCE 6 RF SHDN IN 30k C2 30k 100Ω VCC 5 + PCAP RF DET – 60µA 60µA 150k BIAS GND 2 1 5507 BD C1 = C2 SHDN 1 C2 (µF) ≥ , f = LOWEST RF INPUT FREQUENCY (MHz) 30f
Figure 2.
5507f 4
U U U PI FU CTIO S SHDN (Pin 1):
Shutdown Input. A logic low or no-connect
VCC (Pin 4):
Power Supply Voltage, 2.7V to 6V. VCC should on the SHDN pin places the part in shutdown mode. A logic be bypassed with 0.1µF and 100pF ceramic capacitors. high enables the part. SHDN has an internal 150k pull
PCAP (Pin 5):
Peak Detector Hold Capacitor. Capacitor down resistor to ensure that the part is in shutdown when value is dependent on RF frequency. Capacitor must be the enable driver is in a tri-state condition. connected between PCAP and VCC.
GND (Pin 2):
System Ground.
RFIN (Pin 6):
RF Input Voltage. Referenced to VCC. A
VOUT (Pin 3):
Buffered and Level Shifted Detector Output coupling capacitor must be used to connect to the RF Voltage. signal source. This pin has an internal 250Ω termination and an internal Schottky diode detector.
W BLOCK DIAGRA
VCC 4 GAIN + COMPRESSION BUFFER 3 VOUT C1 250Ω RF – SOURCE 6 RF SHDN IN 30k C2 30k 100Ω VCC 5 + PCAP RF DET – 60µA 60µA 150k BIAS GND 2 1 5507 BD C1 = C2 SHDN 1 C2 (µF) ≥ , f = LOWEST RF INPUT FREQUENCY (MHz) 30f
Figure 2.
5507f 4
