Datasheet ADXL375 (Analog Devices) - 4

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Data Sheet ADXL375 SPECIFICATIONS
TA = 25°C, VS = 2.5 V, VDD I/O = 2.5 V, acceleration = 0 g, CS = 10 µF tantalum, CI/O = 0.1 µF, output data rate (ODR) = 800 Hz, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ1 Max Unit
SENSOR INPUT Each axis Measurement Range2 ±180 ±200 g Nonlinearity Percentage of full scale ±0.25 % Cross-Axis Sensitivity3 ±2.5 % SENSITIVITY Each axis Sensitivity at X 2, 4 OUT, YOUT, ZOUT ODR ≤ 800 Hz 18.4 20.5 22.6 LSB/g Scale Factor at X 2, 4 OUT, YOUT, ZOUT ODR ≤ 800 Hz 44 49 54 mg/LSB Sensitivity Change Due to Temperature ±0.02 %/°C 0 g OFFSET Each axis 0 g Output for XOUT, YOUT, ZOUT −6000 ±400 +6000 mg 0 g Offset vs. Temperature ±10 mg/°C NOISE X-, y-, and z-axes 5 mg/√Hz OUTPUT DATA RATE AND BANDWIDTH5 User selectable Output Data Rate (ODR)4, 6 0.1 3200 Hz SELF-TEST7 Output Change in Z-Axis 6.4 g POWER SUPPLY Operating Voltage Range (VS) 2.0 2.5 3.6 V Interface Voltage Range (VDD I/O) 1.7 1.8 VS V Supply Current Measurement Mode ODR ≥ 100 Hz 145 µA ODR ≤ 3 Hz 35 µA Standby Mode 0.1 µA Turn-On and Wake-Up Time8 ODR = 3200 Hz 1.4 ms TEMPERATURE Operating Temperature Range −40 +85 °C WEIGHT Device Weight 30 mg 1 Typical specifications are for at least 68% of the population of parts and are based on the worst case of mean ± 1 σ distribution, except for sensitivity, which represents the target value. 2 Minimum and maximum specifications represent the worst case of mean ± 3 σ distribution and are not guaranteed in production. 3 Cross-axis sensitivity is defined as coupling between any two axes. 4 The output format for the 1600 Hz and 3200 Hz output data rates is different from the output format for the other output data rates. For more information, see the Data Formatting at Output Data Rates of 3200 Hz and 1600 Hz section. 5 Bandwidth is the −3 dB frequency and is half the output data rate: bandwidth = ODR/2. 6 Output data rates < 6.25 Hz exhibit additional offset shift with increased temperature. 7 Self-test change is defined as the output (g) when the SELF_TEST bit = 1 (DATA_FORMAT register, Address 0x31) minus the output (g) when the SELF_TEST bit = 0. Due to device filtering, the output reaches its final value after 4 × τ when enabling or disabling self-test, where τ = 1/(data rate). For the self-test to operate correctly, the part must be in normal power operation (LOW_POWER bit = 0 in the BW_RATE register, Address 0x2C). 8 Turn-on and wake-up times are determined by the user-defined bandwidth. At a 100 Hz data rate, the turn-on and wake-up times are each approximately 11.1 ms. For other data rates, the turn-on and wake-up times are each approximately τ + 1.1 ms, where τ = 1/(data rate). Rev. B | Page 3 of 32 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Soldering Profile Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Power Sequencing Current Consumption and Output Data Rate Power Saving Modes Low Power Mode Autosleep Mode Standby Mode FIFO Buffer Bypass Mode FIFO Mode Stream Mode Trigger Mode Retrieving Data from the FIFO Buffer Self-Test Interrupts Enabling and Disabling Interrupts Clearing Interrupts Bits in the Interrupt Registers DATA_READY Bit SINGLE_SHOCK Bit DOUBLE_SHOCK Bit Activity Bit Inactivity Bit Watermark Bit Overrun Bit Serial Communications SPI Mode Preventing Bus Traffic Errors I2C Mode Register Map Register Descriptions Register 0x00—DEVID (Read Only) Register 0x1D—THRESH_SHOCK (Read/Write) Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write) Register 0x21—DUR (Read/Write) Register 0x22—Latent (Read/Write) Register 0x23—Window (Read/Write) Register 0x24—THRESH_ACT (Read/Write) Register 0x25—THRESH_INACT (Read/Write) Register 0x26—TIME_INACT (Read/Write) Register 0x27—ACT_INACT_CTL (Read/Write) ACT AC/DC and INACT AC/DC Bits ACT_x Enable and INACT_x Enable Bits Register 0x2A—SHOCK_AXES (Read/Write) Suppress Bit SHOCK_x Enable Bits Register 0x2B—ACT_SHOCK_STATUS (Read Only) ACT_x Source and SHOCK_x Source Bits Asleep Bit Register 0x2C—BW_RATE (Read/Write) LOW_POWER Bit Rate Bits Register 0x2D—POWER_CTL (Read/Write) Link Bit AUTO_SLEEP Bit Measure Bit Sleep Bit Wakeup Bits Register 0x2E—INT_ENABLE (Read/Write) Register 0x2F—INT_MAP (Read/Write) Register 0x30—INT_SOURCE (Read Only) Register 0x31—DATA_FORMAT (Read/Write) SELF_TEST Bit SPI Bit INT_INVERT Bit Justify Bit Register 0x32 to Register 0x37—DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) Register 0x38—FIFO_CTL (Read/Write) FIFO_MODE Bits Trigger Bit Samples Bits Register 0x39—FIFO_STATUS (Read Only) FIFO_TRIG Bit Entries Bits Applications Information Power Supply Decoupling Mechanical Considerations for Mounting Shock Detection Threshold Detection and Bandwidth Link Mode Sleep Mode vs. Low Power Mode Offset Calibration Data Formatting at Output Data Rates of 3200 Hz and 1600 Hz Using Self-Test Axes of Acceleration Sensitivity Layout and Design Recommendations Package Information Outline Dimensions Ordering Guide