Datasheet ADIS16375 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Low Profile, Low Noise Six Degrees of Freedom Inertial Sensor |
| Pages / Page | 29 / 7 — ADIS16375. Data Sheet. TIMING SPECIFICATIONS. Table 2. Normal Mode. … |
| Revision | E |
| File Format / Size | PDF / 795 Kb |
| Document Language | English |
ADIS16375. Data Sheet. TIMING SPECIFICATIONS. Table 2. Normal Mode. Parameter. Description. Min1. Typ. Max. Unit. Timing Diagrams. CHS. tCLS. tSFS
Model Line for this Datasheet
Text Version of Document
ADIS16375 Data Sheet TIMING SPECIFICATIONS
TA = 25°C, VDD = 3.3 V, unless otherwise noted.
Table 2. Normal Mode Parameter Description Min1 Typ Max Unit
fSCLK Serial clock 0.01 15 MHz tSTALL Stall period between data 2 µs tCLS Serial clock low period 31 ns tCHS Serial clock high period 31 ns t Chip select to clock edge 32 ns CS tDAV DOUT valid after SCLK edge 10 ns tDSU DIN setup time before SCLK rising edge 2 ns tDHD DIN hold time after SCLK rising edge 2 ns tDR, tDF DOUT rise/fall times, ≤100 pF loading 3 8 ns tDSOE CS assertion to data out active 0 11 ns tHD SCLK edge to data out invalid 0 ns tSFS Last SCLK edge to CS deassertion 32 ns tDSHI CS deassertion to data out high impedance 0 9 ns t1 Input sync pulse width 5 µs t2 Input sync to data-ready output 430 µs t3 Input sync period 440 µs 1 Guaranteed by design and characterization but not tested in production.
Timing Diagrams CS t t CS CHS tCLS tSFS 1 2 3 4 5 6 15 16 SCLK t t DSOE DAV tHD tDSHI DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB t t DSU DHD DIN R/W A6 A5 A4 A3 A2 D2 D1 LSB
002 09389- Figure 2. SPI Timing and Sequence
tSTALL CS SCLK
003 09389- Figure 3. Stall Time and Data Rate
t3 t2 t1 SYNC CLOCK (CLKIN) DATA READY OUTPUT
004
DATA VALID DATA VALID REGISTERS
09389- Figure 4. Input Clock Timing Diagram Rev. D | Page 6 of 28 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Basic Operation Register Structure SPI Communication Device Configuration Dual Memory Structure Reading Sensor Data User Registers Output Data Registers Inertial Sensor Data Format Rotation Rate (Gyroscope) Acceleration Delta Angles Velocity Changes Internal Temperature Status/Alarm Indicators Product Identification Digital Signal Processing Sampling Plan Averaging/Decimation Filter FIR Filter Banks Filter Memory Organization Default Filter Performance Calibration Manual Bias Correction Manual Sensitivity Correction Bias Null Command Restoring Factory Calibration Linear Acceleration on Effect on Gyroscope Bias Point of Percussion Alignment Alarms Static Alarm Use Dynamic Alarm Use Alarm Reporting Alarm Example System Controls Global Commands Software Reset Automatic Self Test Memory Management Flash Memory Test General-Purpose I/O Data-Ready Indicator Input Sync/Clock Control General-Purpose I/O Control Power Management Real-Time Clock Configuration/Data Applications Information Mounting Tips Evaluation Tools Breakout Board, ADIS16IMU/PCBZ PC-Based Evaluation, EVAL-ADIS2 Power Supply Considerations Outline Dimensions Ordering Guide
TA = 25°C, VDD = 3.3 V, unless otherwise noted.
Table 2. Normal Mode Parameter Description Min1 Typ Max Unit
fSCLK Serial clock 0.01 15 MHz tSTALL Stall period between data 2 µs tCLS Serial clock low period 31 ns tCHS Serial clock high period 31 ns t Chip select to clock edge 32 ns CS tDAV DOUT valid after SCLK edge 10 ns tDSU DIN setup time before SCLK rising edge 2 ns tDHD DIN hold time after SCLK rising edge 2 ns tDR, tDF DOUT rise/fall times, ≤100 pF loading 3 8 ns tDSOE CS assertion to data out active 0 11 ns tHD SCLK edge to data out invalid 0 ns tSFS Last SCLK edge to CS deassertion 32 ns tDSHI CS deassertion to data out high impedance 0 9 ns t1 Input sync pulse width 5 µs t2 Input sync to data-ready output 430 µs t3 Input sync period 440 µs 1 Guaranteed by design and characterization but not tested in production.
Timing Diagrams CS t t CS CHS tCLS tSFS 1 2 3 4 5 6 15 16 SCLK t t DSOE DAV tHD tDSHI DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB t t DSU DHD DIN R/W A6 A5 A4 A3 A2 D2 D1 LSB
002 09389- Figure 2. SPI Timing and Sequence
tSTALL CS SCLK
003 09389- Figure 3. Stall Time and Data Rate
t3 t2 t1 SYNC CLOCK (CLKIN) DATA READY OUTPUT
004
DATA VALID DATA VALID REGISTERS
09389- Figure 4. Input Clock Timing Diagram Rev. D | Page 6 of 28 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Basic Operation Register Structure SPI Communication Device Configuration Dual Memory Structure Reading Sensor Data User Registers Output Data Registers Inertial Sensor Data Format Rotation Rate (Gyroscope) Acceleration Delta Angles Velocity Changes Internal Temperature Status/Alarm Indicators Product Identification Digital Signal Processing Sampling Plan Averaging/Decimation Filter FIR Filter Banks Filter Memory Organization Default Filter Performance Calibration Manual Bias Correction Manual Sensitivity Correction Bias Null Command Restoring Factory Calibration Linear Acceleration on Effect on Gyroscope Bias Point of Percussion Alignment Alarms Static Alarm Use Dynamic Alarm Use Alarm Reporting Alarm Example System Controls Global Commands Software Reset Automatic Self Test Memory Management Flash Memory Test General-Purpose I/O Data-Ready Indicator Input Sync/Clock Control General-Purpose I/O Control Power Management Real-Time Clock Configuration/Data Applications Information Mounting Tips Evaluation Tools Breakout Board, ADIS16IMU/PCBZ PC-Based Evaluation, EVAL-ADIS2 Power Supply Considerations Outline Dimensions Ordering Guide
