Datasheet KSZ8794CNX (Microchip) - 10
| Manufacturer | Microchip |
| Description | Integrated 4-Port 10/100 Managed Ethernet Switch with Gigabit RGMII/MII/RMII Interface |
| Pages / Page | 124 / 10 — KSZ8794CNX. TABLE 2-1:. SIGNALS - KSZ8794CNX (CONTINUED). Pin. Type. … |
| File Format / Size | PDF / 1.7 Mb |
| Document Language | English |
KSZ8794CNX. TABLE 2-1:. SIGNALS - KSZ8794CNX (CONTINUED). Pin. Type. Port. Description. Number. Name. Note 2-1. Note:
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KSZ8794CNX TABLE 2-1: SIGNALS - KSZ8794CNX (CONTINUED) Pin Pin Type Port Description Number Name Note 2-1
52 SPIQ Ipd/O All SPI Serial Data Output in SPI Slave Mode Strap Option: Serial Bus Configuration PD = SPI slave mode. PU = MDC/MDIO mode.
Note:
An external pull-up or pull-down resistor is required. 53 SCL_MDC Ipu All Clock for SPI or MDC/MDIO Interfaces Input clock up to 50 MHz in SPI slave mode. Input clock up to 25 MHz in MDC/MDIO for MIIM access. 54 SDA_MDIO Ipu/O All Data Line for SPI or MDC/MDIO Interfaces Serial data input in SPI slave mode. MDC/MDIO interface input/output data line. 55 SPIS_N Ipu All SPI Interface Chip Select When SPIS_N is high, the KSZ8794CNX is deselected and SPIQ is held in the high impedance state. A high-to-low transi- tion initiates the SPI data transfer. This pin is active-low. 56 VDDIO P — 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry. 57 GNDD GND — Digital Ground. 58 RST_N Ipu — Reset This active-low signal resets the hardware in the device. See the timing requirements in the Timing Diagram Section. 59 VDD12D P — 1.2V Core Power. 60 VDDAT P — 3.3V or 2.5V Analog Power. 61 ISET — — Transmit Output Current Set This pin configures the physical transmit output current. It should be connected to GND through a 12.4 kΩ 1% resistor. 62 GNDA GND — Analog Ground. 63 XI I — Crystal Clock Input/Oscillator Input When using a 25 MHz crystal, this input is connected to one end of the crystal circuit. When using a 3.3V oscillator, this is the input from the oscillator. The crystal or oscillator should have a tolerance of ±50 ppm. 64 XO O — Crystal Clock Output. When using a 25 MHz crystal, this output is connected to one end of the crystal circuit.
Note 2-1
P = power supply; GND = ground; I = input; O = output I/O = bi-directional Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. OTRI = Output tri-stated. PU = Strap pin pull-up. PD = Strap pin pull-down. NC = No connect or tie-to-ground for this product. DS00002134A-page 10 2016 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer (PHY) 3.2 Media Access Controller (MAC) Operation 3.3 Switch Core 3.4 Power and Power Management 3.5 Interfaces 3.6 Advanced Functionality 4.0 Device Registers 4.1 Register Map 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 PME Indirect Registers 4.8 ACL Rule Table and ACL Indirect Registers 4.9 EEE Indirect Registers 4.10 Management Information Base (MIB) Counters 4.11 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Diagrams 8.0 Reset Circuit 9.0 Selection of Isolation Transformer 10.0 Selection of Reference Crystal 11.0 Package Outlines
52 SPIQ Ipd/O All SPI Serial Data Output in SPI Slave Mode Strap Option: Serial Bus Configuration PD = SPI slave mode. PU = MDC/MDIO mode.
Note:
An external pull-up or pull-down resistor is required. 53 SCL_MDC Ipu All Clock for SPI or MDC/MDIO Interfaces Input clock up to 50 MHz in SPI slave mode. Input clock up to 25 MHz in MDC/MDIO for MIIM access. 54 SDA_MDIO Ipu/O All Data Line for SPI or MDC/MDIO Interfaces Serial data input in SPI slave mode. MDC/MDIO interface input/output data line. 55 SPIS_N Ipu All SPI Interface Chip Select When SPIS_N is high, the KSZ8794CNX is deselected and SPIQ is held in the high impedance state. A high-to-low transi- tion initiates the SPI data transfer. This pin is active-low. 56 VDDIO P — 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry. 57 GNDD GND — Digital Ground. 58 RST_N Ipu — Reset This active-low signal resets the hardware in the device. See the timing requirements in the Timing Diagram Section. 59 VDD12D P — 1.2V Core Power. 60 VDDAT P — 3.3V or 2.5V Analog Power. 61 ISET — — Transmit Output Current Set This pin configures the physical transmit output current. It should be connected to GND through a 12.4 kΩ 1% resistor. 62 GNDA GND — Analog Ground. 63 XI I — Crystal Clock Input/Oscillator Input When using a 25 MHz crystal, this input is connected to one end of the crystal circuit. When using a 3.3V oscillator, this is the input from the oscillator. The crystal or oscillator should have a tolerance of ±50 ppm. 64 XO O — Crystal Clock Output. When using a 25 MHz crystal, this output is connected to one end of the crystal circuit.
Note 2-1
P = power supply; GND = ground; I = input; O = output I/O = bi-directional Ipu = Input w/internal pull-up. Ipd = Input w/internal pull-down. Ipd/O = Input w/internal pull-down during reset, output pin otherwise. Ipu/O = Input w/internal pull-up during reset, output pin otherwise. OTRI = Output tri-stated. PU = Strap pin pull-up. PD = Strap pin pull-down. NC = No connect or tie-to-ground for this product. DS00002134A-page 10 2016 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer (PHY) 3.2 Media Access Controller (MAC) Operation 3.3 Switch Core 3.4 Power and Power Management 3.5 Interfaces 3.6 Advanced Functionality 4.0 Device Registers 4.1 Register Map 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 PME Indirect Registers 4.8 ACL Rule Table and ACL Indirect Registers 4.9 EEE Indirect Registers 4.10 Management Information Base (MIB) Counters 4.11 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Diagrams 8.0 Reset Circuit 9.0 Selection of Isolation Transformer 10.0 Selection of Reference Crystal 11.0 Package Outlines
