Datasheet KS8995E (Microchip)
| Manufacturer | Microchip |
| Description | 5-Port 10/100 Integrated Switch with PHY and Frame Buffer |
| Pages / Page | 41 / 1 — KS8995E Micrel KS8995E. 5-Port 10/100 Integrated Switch with PHY and … |
| File Format / Size | PDF / 201 Kb |
| Document Language | English |
KS8995E Micrel KS8995E. 5-Port 10/100 Integrated Switch with PHY and Frame Buffer. Rev. 1.10
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KS8995E Micrel KS8995E
5-Port 10/100 Integrated Switch with PHY and Frame Buffer
Rev. 1.10
On the media side, the KS8995E supports 10BaseT,
100BaseTX and 100BaseFX as specified by the IEEE 802.3
committee.
Physical signal transmission and reception are enhanced
through use of analog circuitry that makes the design more
efficient and allows for lower power consumption and smaller
chip die size.
The major enhancements from the KS8995 to the KS8995E
are support for VLAN, traffic priority queuing, EEPROM
programming for expanded control, MDI/MDI-X auto crossover.
Data sheets and support documentation can be found on
Micrel’s web site at www.micrel.com. General Description
The KS8995E contains five 10/100 physical layer transceivers, five MAC (Media Access Control) units with an integrated
layer 2 switch. The device runs in two modes. The first mode
is a five port integrated switch and the second is as a five port
switch with the fifth port decoupled from the physical port. In
this mode access to the fifth MAC is provided using an MII
(Media Independent Interface).
Useful configurations include a stand alone five port switch as
well as a four port switch with a routing element connected to
the extra MII port. The additional port is also useful for a public
network interfacing.
The KS8995E is designed to reside in an unmanaged design
not requiring processor intervention. This is achieved through
I/O strapping or EEPROM programming at system reset time. Functional Diagram
Look Up
Engine
(1K Entries) Queue
Management SRAM
Buffers
(32Kx32) Buffer
Management FIFO and Flow Control MAC
1 MAC
2 MAC
3 MAC
4 MAC
5 M
I
I MII / SNI
(exclusive)
External
Interface EEPROM
Interface MTXD[3:0]
MTXEN
MTXER
MII_CLK
MRXD[0]
MRXDV
MCOL S
N
I MTXD[0]
MTXEN MII_CLK TXP[5], TXM[5] TXP[4], TXM[4] SCL
SDA Physical
Transceiver
5 RXP[5], RXM[5] Physical
Transceiver
4 RXP[4], RXM[4] TXP[3], TXM[3] TXP[2], TXM[2] Physical
Transceiver
3 RXP[3], RXM[3] Physical
Transceiver
2 RXP[2], RXM[2] TXP[1], TXM[1] RXP[1], RXM[1] Physical
Transceiver
1 MRXD[3:0]
MRXDV
MCOL LED
and
Programming
Interface LED[1][3:0]
LED[2][3:0]
LED[3][3:0]
LED[4][3:0]
LED[5][3:0] Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com August 2003 1 KS8995E
5-Port 10/100 Integrated Switch with PHY and Frame Buffer
Rev. 1.10
On the media side, the KS8995E supports 10BaseT,
100BaseTX and 100BaseFX as specified by the IEEE 802.3
committee.
Physical signal transmission and reception are enhanced
through use of analog circuitry that makes the design more
efficient and allows for lower power consumption and smaller
chip die size.
The major enhancements from the KS8995 to the KS8995E
are support for VLAN, traffic priority queuing, EEPROM
programming for expanded control, MDI/MDI-X auto crossover.
Data sheets and support documentation can be found on
Micrel’s web site at www.micrel.com. General Description
The KS8995E contains five 10/100 physical layer transceivers, five MAC (Media Access Control) units with an integrated
layer 2 switch. The device runs in two modes. The first mode
is a five port integrated switch and the second is as a five port
switch with the fifth port decoupled from the physical port. In
this mode access to the fifth MAC is provided using an MII
(Media Independent Interface).
Useful configurations include a stand alone five port switch as
well as a four port switch with a routing element connected to
the extra MII port. The additional port is also useful for a public
network interfacing.
The KS8995E is designed to reside in an unmanaged design
not requiring processor intervention. This is achieved through
I/O strapping or EEPROM programming at system reset time. Functional Diagram
Look Up
Engine
(1K Entries) Queue
Management SRAM
Buffers
(32Kx32) Buffer
Management FIFO and Flow Control MAC
1 MAC
2 MAC
3 MAC
4 MAC
5 M
I
I MII / SNI
(exclusive)
External
Interface EEPROM
Interface MTXD[3:0]
MTXEN
MTXER
MII_CLK
MRXD[0]
MRXDV
MCOL S
N
I MTXD[0]
MTXEN MII_CLK TXP[5], TXM[5] TXP[4], TXM[4] SCL
SDA Physical
Transceiver
5 RXP[5], RXM[5] Physical
Transceiver
4 RXP[4], RXM[4] TXP[3], TXM[3] TXP[2], TXM[2] Physical
Transceiver
3 RXP[3], RXM[3] Physical
Transceiver
2 RXP[2], RXM[2] TXP[1], TXM[1] RXP[1], RXM[1] Physical
Transceiver
1 MRXD[3:0]
MRXDV
MCOL LED
and
Programming
Interface LED[1][3:0]
LED[2][3:0]
LED[3][3:0]
LED[4][3:0]
LED[5][3:0] Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com August 2003 1 KS8995E
