Datasheet LAN9313, LAN9313i (Microchip) - 7

LAN9313/LAN9313i 2.0 INTRODUCTION 2.1 General Description
The LAN9313/LAN9313i is a full featured, 3 port 10/100 managed Ethernet switch designed for embedded applications where performance, flexibility, ease of integration and system cost control are required. The LAN9313/LAN9313i com- bines all the functions of a 10/100 switch system, including the switch fabric, packet buffers, buffer manager, media access controllers (MACs), PHY transceivers, and serial management. The LAN9313/LAN9313i complies with the IEEE 802.3 (full/half-duplex 10BASE-T and 100BASE-TX) Ethernet protocol specification and 802.1D/802.1Q network man- agement protocol specifications, enabling compatibility with industry standard Ethernet and Fast Ethernet applications. At the core of the LAN9313/LAN9313i is the high performance, high efficiency 3 port Ethernet switch fabric. The switch fabric contains a 3 port VLAN layer 2 switch engine that supports untagged, VLAN tagged, and priority tagged frames. The switch fabric provides an extensive feature set which includes spanning tree protocol support, multicast packet fil- tering and Quality of Service (QoS) packet prioritization by VLAN tag, destination address, port default value or DIFF- SERV/TOS, allowing for a range of prioritization implementations. 32K of buffer RAM allows for the storage of multiple packets while forwarding operations are completed, and a 1K entry forwarding table provides ample room for MAC address forwarding tables. Each port is allocated a cluster of 4 dynamic QoS queues which allow each queue size to grow and shrink with traffic, effectively utilizing all available memory. This memory is managed dynamically via the buffer manager block within the switch fabric. All aspects of the switch fabric are managed via the switch fabric configuration and status registers, which are indirectly accessible via the system control and status registers. The LAN9313/LAN9313i provides 3 switched ports. Each port is fully compliant with the IEEE 802.3 standard and all internal MACs and PHYs support full/half duplex 10BASE-T and 100BASE-TX operation. The LAN9313/LAN9313i pro- vides 2 on-chip PHYs, 1 Virtual PHY and 3 MACs. The Virtual PHY and the third MAC are used to connect the LAN9313/LAN9313i switch fabric to an external MAC or PHY. All ports support automatic or manual full duplex flow con- trol or half duplex backpressure (forced collision) flow control. 2K jumbo packet (2048 byte) support allows for oversized packet transfers, effectively increasing throughput while deceasing CPU load. All MAC and PHY related settings are fully configurable via their respective registers within the LAN9313/LAN9313i. The integrated SPI, I2C and SMI slave controllers allow for full serial management of the LAN9313/LAN9313i via the integrated SPI/I2C serial interface or MII interface respectively. The inclusion of these interfaces allows for greater flex- ibility in the incorporation of the LAN9313/LAN9313i into various designs. It is this flexibility which allows the LAN9313/LAN9313i to operate in 2 different modes and under various management conditions. In MAC mode, the LAN9313/LAN9313i can be connected to an external PHY via the MII interface. In PHY mode, the LAN9313/LAN9313i can be connected to an external MAC via the MII interface. In both MAC and PHY modes, the LAN9313/LAN9313i can be unmanaged, SMI managed, I2C managed or SPI managed. This flexibility in management makes the LAN9313/LAN9313i a candidate for virtually all switch applications. The LAN9313/LAN9313i contains an I2C/Microwire master EEPROM controller for connection to an optional EEPROM. This allows for the storage and retrieval of static data. The internal EEPROM Loader can be optionally configured to automatically load stored configuration settings from the EEPROM into the LAN9313/LAN9313i at reset, allowing the LAN9313/LAN9313i to operate unmanaged. In addition to the primary functionality described above, the LAN9313/LAN9313i provides additional features designed for extended functionality. These include a configurable 16-bit General Purpose Timer (GPT), a 32-bit 25MHz free run- ning counter, a 12-bit configurable GPIO/LED interface, and IEEE 1588 time stamping on all ports and select GPIOs. The IEEE time stamp unit provides a 64-bit tunable clock for accurate PTP timing and a timer comparator to allow time based interrupt generation. The LAN9313/LAN9313i’s performance, features and small size make it an ideal solution for many applications in the consumer electronics and industrial automation markets. Targeted applications include: set top boxes (cable, satellite and IP), digital televisions, digital video recorders, voice over IP and video phone systems, home gateways, and test and measurement equipment.  2008-2016 Microchip Technology Inc. DS00002288A-page 7 Document Outline 1.0 Preface 1.1 General Terms 1.2 Buffer Types TABLE 1-1: Buffer Types 1.3 Register Nomenclature TABLE 1-2: Register Bit Types 2.0 Introduction 2.1 General Description 2.2 Block Diagram FIGURE 2-1: Internal LAN9313/LAN9313i Block Diagram 2.2.1 System Clocks/Reset/PME Controller 2.2.2 System Interrupt Controller 2.2.3 Switch Fabric 2.2.4 Ethernet PHYs 2.2.5 PHY Management Interface (PMI) 2.2.6 SPI/I2C Slave Controller 2.2.7 SMI Slave Controller 2.2.8 EEPROM Controller/Loader 2.2.9 1588 Time Stamp 2.2.10 GPIO/LED Controller 2.3 Modes of Operation 2.3.1 MAC Mode 2.3.2 PHY Mode 2.3.3 Management Modes TABLE 2-1: LAN9313/LAN9313i Modes FIGURE 2-2: System Block Diagrams - MAC/PHY Modes of Operation 3.0 Pin Description and Configuration 3.1 Pin Diagrams 3.1.1 128-VTQFP Pin Diagram FIGURE 3-1: LAN9313 128-VTQFP Pin Assignments (TOP VIEW) 3.1.2 128-XVTQFP Pin Diagram FIGURE 3-2: LAN9313/LAN9313i 128-XVTQFP Pin Assignments (TOP VIEW) 3.2 Pin Descriptions TABLE 3-1: LAN Port 1 Pins TABLE 3-2: LAN Port 2 Pins TABLE 3-3: LAN Port 1 & 2 Power and Common Pins TABLE 3-4: LAN Port 0(External MII) Pins TABLE 3-5: Dedicated Configuration Strap Pins TABLE 3-6: EEPROM Pins TABLE 3-7: Serial Management Pins TABLE 3-8: Miscellaneous Pins TABLE 3-9: PLL Pins TABLE 3-10: Core and I/O Power and Ground Pins TABLE 3-11: No-Connect Pins 4.0 Clocking, Resets, and Power Management 4.1 Clocks 4.2 Resets TABLE 4-1: Reset Sources and Affected LAN9313/LAN9313i Circuitry 4.2.1 Chip-Level Resets 4.2.2 Multi-Module Resets 4.2.3 Single-Module Resets 4.2.4 Configuration Straps TABLE 4-2: Soft-Strap Configuration Strap Definitions TABLE 4-3: Hard-Strap Configuration Strap Definitions 4.3 Power Management 4.3.1 Port 1 & 2 PHY Power Management 5.0 System Interrupts 5.1 Functional Overview 5.2 Interrupt Sources FIGURE 5-1: Functional Interrupt Register Hierarchy 5.2.1 1588 Time Stamp Interrupts 5.2.2 Switch Fabric Interrupts 5.2.3 Ethernet PHY Interrupts 5.2.4 GPIO Interrupts 5.2.5 General Purpose Timer Interrupt 5.2.6 Software Interrupt 5.2.7 Device Ready Interrupt 6.0 Switch Fabric 6.1 Functional Overview 6.2 Switch Fabric CSRs 6.2.1 Switch Fabric CSR Writes FIGURE 6-1: Switch Fabric CSR Write Access Flow Diagram 6.2.2 Switch Fabric CSR Reads FIGURE 6-2: Switch Fabric CSR Read Access Flow Diagram 6.2.3 Flow Control Enable Logic TABLE 6-1: Switch Fabric Flow Control Enable Logic 6.3 10/100 Ethernet MACs 6.3.1 Receive MAC 6.3.2 Transmit MAC 6.4 Switch Engine (SWE) 6.4.1 MAC Address Lookup Table FIGURE 6-3: ALR Table Entry Structure 6.4.2 Forwarding Rules 6.4.3 Transmit Priority Queue Selection FIGURE 6-4: Switch Engine Transmit Queue Selection FIGURE 6-5: Switch Engine Transmit Queue Calculation 6.4.4 VLAN Support TABLE 6-2: VLAN Table Entry Structure 6.4.5 Spanning Tree Support TABLE 6-3: Spanning Tree States 6.4.6 Ingress Flow Metering and Coloring TABLE 6-4: Typical Ingress Rate Settings FIGURE 6-6: Switch Engine Ingress Flow Priority Selection FIGURE 6-7: Switch Engine Ingress Flow Priority Calculation 6.4.7 Broadcast Storm Control TABLE 6-5: Typical Broadcast Rate Settings 6.4.8 IPv4 IGMP Support 6.4.9 Port Mirroring 6.4.10 Host CPU Port Special Tagging 6.4.11 Counters 6.5 Buffer Manager (BM) 6.5.1 Packet Buffer Allocation 6.5.2 Random Early Discard (RED) 6.5.3 Transmit Queues 6.5.4 Transmit Priority Queue Servicing 6.5.5 Egress Rate Limiting (Leaky Bucket) TABLE 6-6: Typical Egress Rate Settings 6.5.6 Adding, Removing, and Changing VLAN Tags FIGURE 6-8: Hybrid Port Tagging and Un-tagging 6.5.7 Counters 6.6 Switch Fabric Interrupts 7.0 Ethernet PHYs 7.1 Functional Overview 7.1.1 PHY Addressing TABLE 7-1: Default PHY Serial MII Addressing 7.2 Port 1 & 2 PHYs FIGURE 7-1: Port x PHY Block Diagram 7.2.1 100BASE-TX Transmit FIGURE 7-2: 100BASE-TX Transmit Data Path TABLE 7-2: 4B/5B Code Table 7.2.2 100BASE-TX Receive FIGURE 7-3: 100BASE-TX Receive Data Path 7.2.3 10BASE-T Transmit 7.2.4 10BASE-T Receive 7.2.5 PHY Auto-negotiation 7.2.6 HP Auto-MDIX FIGURE 7-4: Direct Cable Connection vs. Cross-Over Cable Connection 7.2.7 MII MAC Interface 7.2.8 PHY Management Control TABLE 7-3: PHY Interrupt Sources 7.2.9 PHY Power-Down Modes 7.2.10 PHY Resets 7.2.11 LEDs 7.2.12 Required Ethernet Magnetics 7.3 Virtual PHY 7.3.1 Virtual PHY Auto-Negotiation 7.3.2 Virtual PHY in MAC Modes 7.3.3 Virtual PHY Resets 8.0 Serial Management 8.1 Functional Overview 8.2 I2C/Microwire Master EEPROM Controller TABLE 8-1: I2C/Microwire Master Serial Management Pins Characteristics 8.2.1 EEPROM Controller Operation FIGURE 8-1: EEPROM Access Flow Diagram 8.2.2 I2C EEPROM TABLE 8-2: I2C EEPROM Size Ranges FIGURE 8-2: I2C Cycle FIGURE 8-3: I2C EEPROM Addressing FIGURE 8-4: I2C EEPROM Byte Read FIGURE 8-5: I2C EEPROM Sequential Byte Reads FIGURE 8-6: I2C EEPROM Byte Write 8.2.3 Microwire EEPROM TABLE 8-3: Microwire EEPROM Size Ranges TABLE 8-4: Microwire Command Set for 7 Address Bits TABLE 8-5: Microwire Command Set for 9 Address Bits TABLE 8-6: Microwire Command Set for 11 Address Bits FIGURE 8-7: EEPROM ERASE Cycle FIGURE 8-8: EEPROM ERAL Cycle FIGURE 8-9: EEPROM EWDS Cycle FIGURE 8-10: EEPROM EWEN Cycle FIGURE 8-11: EEPROM READ Cycle FIGURE 8-12: EEPROM WRITE Cycle FIGURE 8-13: EEPROM WRAL Cycle 8.2.4 EEPROM Loader TABLE 8-7: EEPROM Contents Format Overview FIGURE 8-14: EEPROM Loader Flow Diagram TABLE 8-8: EEPROM Configuration Bits 8.3 SPI/I2C Slave Controller TABLE 8-9: SPI / I2C Slave Serial Management Pins Characteristics 8.4 SPI Slave Operation TABLE 8-10: Supported SPI Instructions 8.4.1 SPI Read Sequence FIGURE 8-15: SPI Reads 8.4.2 SPI Write Sequence FIGURE 8-16: SPI Writes 8.5 I2C Slave Operation 8.5.1 I2C Slave Command Format FIGURE 8-17: I2C Slave Addressing 8.5.2 I2C Slave Read Sequence FIGURE 8-18: I2C Slave Reads 8.5.3 I2C Slave Write Sequence FIGURE 8-19: I2C Slave Writes 9.0 MII Management 9.1 Functional Overview 9.2 SMI Slave Controller TABLE 9-1: SMI Frame Format 9.2.1 Read Sequence 9.2.2 Write Sequence 9.3 PHY Management Interface (PMI) TABLE 9-2: MII Management Frame Format 9.3.1 EEPROM Loader PHY Register Access 9.4 MII Mode Multiplexer 9.4.1 MAC Mode Unmanaged FIGURE 9-1: MII Mux Management Path Connections - MAC Mode Unmanaged 9.4.2 MAC Mode SMI Managed FIGURE 9-2: MII Mux Management Path Connections - MAC Mode SMI Managed 9.4.3 MAC Mode I2C/SPI Managed FIGURE 9-3: MII Mux Management Path Connections - MAC Mode I2C/SPI Managed 9.4.4 PHY Mode Unmanaged FIGURE 9-4: MII Mux Management Path Connections - PHY Mode Unmanaged 9.4.5 PHY Mode SMI Managed FIGURE 9-5: MII Mux Management Path Connections - PHY Mode SMI Managed 9.4.6 PHY Mode I2C/SPI Managed FIGURE 9-6: MII Mux Management Path Connections - PHY Mode I2C/SPI Managed 10.0 IEEE 1588 Hardware Time Stamp Unit 10.1 Functional Overview 10.1.1 IEEE 1588 10.1.2 Block Diagram FIGURE 10-1: IEEE 1588 Block Diagram 10.2 IEEE 1588 Time Stamp TABLE 10-1: IEEE 1588 Message Type Detection FIGURE 10-2: IEEE 1588 Message Time Stamp Point TABLE 10-2: Time Stamp Capture Delay 10.2.1 Capture Locking 10.2.2 PTP Message Detection TABLE 10-3: PTP Multicast Addresses 10.3 IEEE 1588 Clock TABLE 10-4: Typical IEEE 1588 Clock Addend Values 10.4 IEEE 1588 Clock/Events 10.5 IEEE 1588 GPIOs 10.6 IEEE 1588 Interrupts 11.0 General Purpose Timer & Free-Running Clock 11.1 General Purpose Timer 11.2 Free-Running Clock 12.0 GPIO/LED Controller 12.1 Functional Overview 12.2 GPIO Operation 12.2.1 GPIO IEEE 1588 Timestamping 12.2.2 GPIO Interrupts 12.3 LED Operation TABLE 12-1: LED Operation as a Function of LED_CFG[9:8] 13.0 Register Descriptions FIGURE 13-1: LAN9313/LAN9313i Base Register Memory Map 13.1 System Control and Status Registers TABLE 13-1: System Control and Status Registers 13.1.1 Interrupts 13.1.2 GPIO/LED 13.1.3 EEPROM 13.1.4 IEEE 1588 13.1.5 Switch Fabric TABLE 13-2: SWITCH_MAC_ADDRL, SWITCH_MAC_ADDRH, and EEPROM Byte Ordering FIGURE 13-2: Example SWITCH_MAC_ADDRL, SWITCH_MAC_ADDRH, and EEPROM Setup TABLE 13-3: Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map 13.1.6 PHY Management Interface (PMI) 13.1.7 Virtual PHY TABLE 13-4: Virtual PHY MII Serially Adressable Register Index TABLE 13-5: Emulated Link Partner Pause Flow Control Ability Default Values TABLE 13-6: Emulated Link Partner Default Advertised Ability 13.1.8 Miscellaneous 13.2 Ethernet PHY Control and Status Registers 13.2.1 Virtual PHY Registers 13.2.2 Port 1 & 2 PHY Registers TABLE 13-7: Port 1 & 2 PHY MII Serially Adressable Registers TABLE 13-8: 10BASE-T Full Duplex Advertisement Default Value TABLE 13-9: 10BASE-T Half Duplex Advertisement Bit Default Value TABLE 13-10: MODE[2:0] Definitions TABLE 13-11: Auto-MDIX Enable and Auto-MDIX State Bit Functionality 13.3 Switch Fabric Control and Status Registers TABLE 13-12: Indirectly Accessible Switch Control and Status Registers 13.3.1 General Switch CSRs 13.3.2 Switch Port 0, Port 1, and Port 2 CSRs 13.3.3 Switch Engine CSRs TABLE 13-13: Metering/Color Table Register Descriptions 13.3.4 Buffer Manager CSRs 14.0 Operational Characteristics 14.1 Absolute Maximum Ratings* 14.2 Operating Conditions** 14.3 Power Consumption TABLE 14-1: Supply and Current (10BASE-T Full-Duplex) TABLE 14-2: Supply and Current (100BASE-TX Full-Duplex) 14.4 DC Specifications TABLE 14-3: I/O Buffer Characteristics TABLE 14-4: 100BASE-TX Transceiver Characteristics TABLE 14-5: 10BASE-T Transceiver Characteristics 14.5 AC Specifications 14.5.1 Equivalent Test Load FIGURE 14-1: Output Equivalent Test Load 14.5.2 Reset and Configuration Strap Timing FIGURE 14-2: nRST Reset Pin Timing TABLE 14-6: nRST Reset Pin Timing Values 14.5.3 Power-On Configuration Strap Valid Timing FIGURE 14-3: Power-On Configuration Strap Latching Timing TABLE 14-7: Power-On Configuration Strap Latching Timing Values 14.5.4 Microwire Timing FIGURE 14-4: Microwire Timing TABLE 14-8: Microwire Timing Values 14.5.5 SPI Slave Timing FIGURE 14-5: SPI Slave Timing TABLE 14-9: SPI Slave Timing Values 14.6 Clock Circuit TABLE 14-10: LAN9313/LAN9313i Crystal Specifications 15.0 Package Outlines 15.1 128-VTQFP Package Outline FIGURE 15-1: 128-vTQFP, 14x14x1.0mm body, 0.4mm Pitch FIGURE 15-2: 128-VTQFP Recommended PCB Land Pattern 15.2 128-XVTQFP Package Outline FIGURE 15-3: 128-XVTQFP 14x14x1.0mm Body, 0.4mm Pitch Appendix A: Data sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service