Datasheet LTC2512-24 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 24-Bit Over-Sampling ADC with Configurable Flat Passband Digital Filter |
| Pages / Page | 38 / 6 — The. denotes the specifications which apply over the full operating |
| File Format / Size | PDF / 709 Kb |
| Document Language | English |
The. denotes the specifications which apply over the full operating
Model Line for this Datasheet
Text Version of Document
LTC2512-24 ADC TIMING CHARACTERISTICS
The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tDSDOBBUSYL SDOB Data Valid Delay from BUSY↓ CL = 20pF (Note 8) l 5 ns tENB Bus Enable Time After RDLB↓ (Note 13) l 16 ns tDISB Bus Relinquish Time After RDLB↑ (Note 13) 13 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 8:
Guaranteed by design, not subject to test. may cause permanent damage to the device. Exposure to any Absolute
Note 9:
Bipolar zero-scale error is the offset voltage measured from Maximum Rating condition for extended periods may affect device –0.5LSB when the output code flickers between 0000 0000 0000 0000 reliability and lifetime. 0000 0000 and 1111 1111 1111 1111 1111 1111. Full-scale bipolar error
Note 2:
All voltage values are with respect to ground. is the worst-case of –FS or +FS untrimmed deviation from ideal first and
Note 3:
When these pin voltages are taken below ground or above REF or last code transitions and includes the effect of offset error. OVDD, they will be clamped by internal diodes. This product can handle
Note 10:
All specifications in dB are referred to a full-scale ±5V input with input currents up to 100mA below ground or above REF or OVDD without a 5V reference voltage. latch-up.
Note 11:
fSMPL = 1.6MHz, IREF varies proportionally with sample rate.
Note 4:
VDD = 2.5V, OVDD = 2.5V, REF = 5V, VCM = 2.5V, fSMPL = 1.6MHz,
Note 12:
fSMPL and fDRB are specified with only shifting out the 14-bit DF = 4. differential result. Shifting out the 8-bit common-mode result requires
Note 5:
Recommended operating conditions. additional I/O time resulting in maximum sampling and output data rates
Note 6:
Transition noise is defined as the noise level of the ADC with IN+ of 1.42Msps. and IN– shorted.
Note 13:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
Note 7:
Integral nonlinearity is defined as the deviation of a code from a and OVDD = 5.25V. straight line passing through the actual endpoints of the transfer curve.
Note 14:
tSCKA, tSCKB of 10ns maximum allows a shift clock frequency up The deviation is measured from the center of the quantization band. to 100MHz for rising edge capture. 0.8•OVDD tWIDTH 0.2•OVDD t t 50% 50% DELAY DELAY 251224 F01 0.8•OVDD 0.8•OVDD 0.2•OVDD 0.2•OVDD
Figure 1. Voltage Levels for Specifications
251224fa 6 For more information www.linear.com/LTC2512-24
The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tDSDOBBUSYL SDOB Data Valid Delay from BUSY↓ CL = 20pF (Note 8) l 5 ns tENB Bus Enable Time After RDLB↓ (Note 13) l 16 ns tDISB Bus Relinquish Time After RDLB↑ (Note 13) 13 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 8:
Guaranteed by design, not subject to test. may cause permanent damage to the device. Exposure to any Absolute
Note 9:
Bipolar zero-scale error is the offset voltage measured from Maximum Rating condition for extended periods may affect device –0.5LSB when the output code flickers between 0000 0000 0000 0000 reliability and lifetime. 0000 0000 and 1111 1111 1111 1111 1111 1111. Full-scale bipolar error
Note 2:
All voltage values are with respect to ground. is the worst-case of –FS or +FS untrimmed deviation from ideal first and
Note 3:
When these pin voltages are taken below ground or above REF or last code transitions and includes the effect of offset error. OVDD, they will be clamped by internal diodes. This product can handle
Note 10:
All specifications in dB are referred to a full-scale ±5V input with input currents up to 100mA below ground or above REF or OVDD without a 5V reference voltage. latch-up.
Note 11:
fSMPL = 1.6MHz, IREF varies proportionally with sample rate.
Note 4:
VDD = 2.5V, OVDD = 2.5V, REF = 5V, VCM = 2.5V, fSMPL = 1.6MHz,
Note 12:
fSMPL and fDRB are specified with only shifting out the 14-bit DF = 4. differential result. Shifting out the 8-bit common-mode result requires
Note 5:
Recommended operating conditions. additional I/O time resulting in maximum sampling and output data rates
Note 6:
Transition noise is defined as the noise level of the ADC with IN+ of 1.42Msps. and IN– shorted.
Note 13:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
Note 7:
Integral nonlinearity is defined as the deviation of a code from a and OVDD = 5.25V. straight line passing through the actual endpoints of the transfer curve.
Note 14:
tSCKA, tSCKB of 10ns maximum allows a shift clock frequency up The deviation is measured from the center of the quantization band. to 100MHz for rising edge capture. 0.8•OVDD tWIDTH 0.2•OVDD t t 50% 50% DELAY DELAY 251224 F01 0.8•OVDD 0.8•OVDD 0.2•OVDD 0.2•OVDD
Figure 1. Voltage Levels for Specifications
251224fa 6 For more information www.linear.com/LTC2512-24
