Data SheetAD5750/AD5750-1/AD5750-2FUNCTIONAL BLOCK DIAGRAMDVCC GNDAVDD GND COMP1 COMP2CLEARAD5750/AD5750-1/AD5750-2CLRSELVSENSE+SCLK/OUTEN*INPUT SHIFTSDIN/R0*REGISTERVOUT RANGEANDVOUTSYNC/RSET*SCALINGCONTROLSDO/VFAULT*LOGICVOUTSHORT FAULTHW SELECTSTATUSVSENSE–REGISTERVINR2VR3DDVREFRESETIOUT RANGEREXT1SCALINGREXT2RSETIOUTVx**OVERTEMPVSSFAULT/ TEMP*VOUT SHORT FAULTIOUT OPEN FAULTNC/IFAULT*POWER-IOUTON RESETOPEN FAULTAD2/R1*AD1/R2*AD0/R3*AVSS* DENOTES SHARED PIN. SOFTWARE MODE DENOTED BY REGULAR TEXT, HARDWARE MODEDENOTED BY ITALICTEXT. FOR EXAMPLE, FOR FAULT/ TEMPPIN, IN SOFTWARE MODE, THIS PIN TAKES ON FAULT FUNCTION. IN HARDWARE MODE, THIS PIN TAKES ON TEMPFUNCTION. 001 ** Vx IS AN INTERNAL BIAS VOLTAGE (CAN BE GROUND OR OTHER VOLTAGE) THAT IS USEDTO GENERATE THE INTERNAL SENSE CURRENTS NEEDED FOR THE CURRENT OUTPUTS. 07268- Figure 1. Rev. F | Page 3 of 36 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications Timing Characteristics Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Voltage Output Current Output Terminology Theory of Operation Software Mode Current Output Architecture Driving Inductive Loads Voltage Output Amplifier Driving Large Capacitive Loads Power-On State of AD5750/AD5750-1/AD5750-2 Default Registers at Power-On Reset Function OUTEN Software Control Input Shift Register Status Bit Read Operation Hardware Control Transfer Function Detailed Description of Features Output Fault Alert—Software Mode Output Fault Alert—Hardware Mode Voltage Output Short-Circuit Protection Asynchronous Clear (CLEAR) External Current Setting Resistor Programmable Overrange Modes Packet Error Checking Applications Information Transient Voltage Protection Thermal Considerations Layout Guidelines Galvanically Isolated Interface Microprocessor Interfacing Outline Dimensions Ordering Guide