Datasheet HMC905LP3E (Analog Devices)

HMC905LP3E
v01.0414
6 GHz LOW NOISE PROGRAMMABLE DIVIDER (N = 1 to 4) Typical Applications Features
4 The HMC905LP3E is ideal for: Low Noise Floor: -164 dBc/Hz at 10 MHz Offset for N = 4 4 • LO Generation with Low Noise Floor Programmable Frequency Divider, N = 1, 2, 3 or 4 T • Software Defined Radios 400 MHz to 6 GHz Input Frequency Range T M • Clock Generators Up to +6 dBm Output Power M • Fast Switching Synthesizers Sleep Mode: Consumes <1 µA • Military Applications S - S 16 Lead 3X3 mm SMT Package: 9mm2 • Test Equipment S - S R • Sensors R O O T
Functional Diagram General Description
T C C E The HMC905LP3E is a SiGe BiCMOS low noise E T programmable frequency divider in a 3x3 mm lead- T E less surface mount package. The circuit can be pro- E grammed to divide from N = 1 to N = 4 in the 400 MHz to 6 GHz input frequency range. The high level out- put power (up to 6 dBm single ended) with a very low S & D SSB phase noise and 50% duty cycle makes this S & D R device ideal for low noise clock generation, LO R E generation and LO drive applications. Configurable E ID bias and output power controls al ow current consumption and output power control. The device ID IV incorporates a power down feature, good input IV to output isolation and fast start up time. The Y D HMC905LP3E can be included into fast switching “ping-pong” applications. Y D C C N N E E U
Electrical Specifications, T = +25° C, Vcc = +3.3V, Z A o = 50Ω
U Q Parameter Conditions Min. Typ. Max. Units Q E
RF Input Characteristics
E R RF Input Frequency Single-ended input 400 6000[1] MHz R F RF Input Power Single-ended input 0 6 10 dBm F
Divider Output Characteristics
-Typically, 50 ohms load resistors connected to Vcc Output Power (Single-ended Out) - 1 bit programmable (CTRL digital signal) [2] -2 3 6 dBm SSB Phase Noise @ 10 kHz Offset -150 dBc/Hz +6 dBm Input Power, 6 GHz input, SSB Phase Noise @ 100 kHz Offset -158 dBc/Hz Single-Ended Input and Output, Divide-by-4 [3] SSB Phase Noise @ 10 MHz Offset -164 dBc/Hz Start Up Time EN bit from OFF to ON State (0V to Vcc) 200 ns Power Down Time EN bit from ON to OFF State (Vcc to 0V) 20 ns Delay from divide ratio change Setting Time at Division Ratio Change 25 ns to output frequency change [1] Maximum 5500 MHz in Divide by 2. [2] See typical supply currents vs. BIAS0, BIAS1, CTRL bits table [3] See Residual Phase Noise plot Info F rmoatr p ion rfiurcne is , d hed ebly ivAe n r al y a og D n evd t ice o p s is bla eli c eve o ed t rd o b e e ras: H ccuratite tiatne M d reli iac bl reo . w Ho av wev e C er, n o o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rporation, 20 Alpha Road, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 978-250-3343 Fax: 978-250-3373 O rights of third parties that may result from its use. Specifications subject to change without notice. No P rd hone e r O : 7 n 81- -3li 2n 9 e a -47 t w 0 w 0 • O w rd .h e it r o t niltie n .c e ao t m
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