Datasheet LT8315 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 560VIN Micropower No-Opto Isolated Flyback Converter with 630V/300mA Switch |
| Pages / Page | 24 / 7 — PIN FUNCTIONS DRAIN (Pins 1,2,3):. IREG/SS (Pin 14):. INTV. CC (Pin 8):. … |
| File Format / Size | PDF / 1.6 Mb |
| Document Language | English |
PIN FUNCTIONS DRAIN (Pins 1,2,3):. IREG/SS (Pin 14):. INTV. CC (Pin 8):. SMODE (Pin 16):. BIAS (Pin 9):. EN/UVLO (Pin 17):
Model Line for this Datasheet
Text Version of Document
LT8315
PIN FUNCTIONS DRAIN (Pins 1,2,3):
Drain of the 630V Internal Power
IREG/SS (Pin 14):
Current Regulation/Soft-Start Pin. A Switch and Startup FET. Design a compact layout with the 10μA current flows out of this pin. The resulting voltage transformer and input capacitor, and minimize trace area sets the output current regulation point, as determined by to reduce EMI and voltage spikes. an internal current regulation loop. Program the current
INTV
with a resistor to GND, or connect a capacitor to imple-
CC (Pin 8):
Internal Gate Driver Bias Voltage. During start-up, current from the DRAIN charges this pin to 12V. ment soft-start. During operation, a linear regulator from BIAS maintains
SMODE (Pin 16):
Standby Mode Pin. Connect this pin to this voltage at 10V. Bypass locally with a ≥2.2μF ceramic INTVCC to enable Standby Mode, which reduces the mini- ≥15V capacitor. mum switching frequency to 220Hz for ultralow quiescent
BIAS (Pin 9):
Unregulated Input Voltage for the IC. This pin power consumption. Connect to GND to disable. derives power from a third winding on the transformer to
EN/UVLO (Pin 17):
Enable/Undervoltage Lockout Pin. The provide power to INTVCC. Bypass locally with a capacitor. chip will operate only if the voltage on this pin is greater
DCM (Pin 10):
Discontinuous Conduction Mode Detec- than the internal 1.22V reference voltage. Connect to a tor. This pin detects the dV/dt of the switching waveform, resistor divider as desired, or connect to BIAS or INTVCC ensuring accurate output voltage sampling and quasi- if UVLO functionality is not desired. resonant boundary-mode switching. Connect a capacitor
SOURCE (Pin 18):
Source of 630V Internal Power Switch. with series resistance from this pin to the third winding. The voltage appearing on this pin is used for peak current-
TC (Pin 11):
Temperature Compensation Pin. This pin mode control and current limiting. Connect a current- presents a proportional-to-absolute-temperature (PTAT) sensing resistor to GND to program the current limit. voltage, which is equal to the internal 1.22V reference Design a compact layout with the transformer and input voltage at 25°C and rises with temperature by 4.1mV/°C, capacitor to reduce EMI and voltage spikes. to compensate for the output rectifier diode. Connect an
NC (Pin 19):
No-Connect. This pin is electrically dis- appropriate resistor from this pin to FB. connected. Leave floating.
FB (Pin 12):
FeedBack Pin. The voltage appearing on this
GND (Pins 15, 20, 21):
Ground.
Solder the exposed pad
pin is sampled and regulated to equal the internal 1.22V
(Pin 21) to a ground plane for heat sinking.
reference voltage. Connect this pin to a resistor divider from the third winding to regulate the output voltage.
VC (Pin 13):
Loop Compensation Pin. An internal GM transconductance amplifier feeds this pin with an error current depending on the sampled FB voltage. The result- ing voltage determines the switching frequency and peak current limit for power delivery. Connect a series R-C network to stabilize the regulator. 8315fa For more information www.linear.com/LT8315 7 Document Outline FEATURES APPLICATIONS DESCRIPTION TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM OPERATION APPLICATIONS INFORMATION PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS
PIN FUNCTIONS DRAIN (Pins 1,2,3):
Drain of the 630V Internal Power
IREG/SS (Pin 14):
Current Regulation/Soft-Start Pin. A Switch and Startup FET. Design a compact layout with the 10μA current flows out of this pin. The resulting voltage transformer and input capacitor, and minimize trace area sets the output current regulation point, as determined by to reduce EMI and voltage spikes. an internal current regulation loop. Program the current
INTV
with a resistor to GND, or connect a capacitor to imple-
CC (Pin 8):
Internal Gate Driver Bias Voltage. During start-up, current from the DRAIN charges this pin to 12V. ment soft-start. During operation, a linear regulator from BIAS maintains
SMODE (Pin 16):
Standby Mode Pin. Connect this pin to this voltage at 10V. Bypass locally with a ≥2.2μF ceramic INTVCC to enable Standby Mode, which reduces the mini- ≥15V capacitor. mum switching frequency to 220Hz for ultralow quiescent
BIAS (Pin 9):
Unregulated Input Voltage for the IC. This pin power consumption. Connect to GND to disable. derives power from a third winding on the transformer to
EN/UVLO (Pin 17):
Enable/Undervoltage Lockout Pin. The provide power to INTVCC. Bypass locally with a capacitor. chip will operate only if the voltage on this pin is greater
DCM (Pin 10):
Discontinuous Conduction Mode Detec- than the internal 1.22V reference voltage. Connect to a tor. This pin detects the dV/dt of the switching waveform, resistor divider as desired, or connect to BIAS or INTVCC ensuring accurate output voltage sampling and quasi- if UVLO functionality is not desired. resonant boundary-mode switching. Connect a capacitor
SOURCE (Pin 18):
Source of 630V Internal Power Switch. with series resistance from this pin to the third winding. The voltage appearing on this pin is used for peak current-
TC (Pin 11):
Temperature Compensation Pin. This pin mode control and current limiting. Connect a current- presents a proportional-to-absolute-temperature (PTAT) sensing resistor to GND to program the current limit. voltage, which is equal to the internal 1.22V reference Design a compact layout with the transformer and input voltage at 25°C and rises with temperature by 4.1mV/°C, capacitor to reduce EMI and voltage spikes. to compensate for the output rectifier diode. Connect an
NC (Pin 19):
No-Connect. This pin is electrically dis- appropriate resistor from this pin to FB. connected. Leave floating.
FB (Pin 12):
FeedBack Pin. The voltage appearing on this
GND (Pins 15, 20, 21):
Ground.
Solder the exposed pad
pin is sampled and regulated to equal the internal 1.22V
(Pin 21) to a ground plane for heat sinking.
reference voltage. Connect this pin to a resistor divider from the third winding to regulate the output voltage.
VC (Pin 13):
Loop Compensation Pin. An internal GM transconductance amplifier feeds this pin with an error current depending on the sampled FB voltage. The result- ing voltage determines the switching frequency and peak current limit for power delivery. Connect a series R-C network to stabilize the regulator. 8315fa For more information www.linear.com/LT8315 7 Document Outline FEATURES APPLICATIONS DESCRIPTION TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM OPERATION APPLICATIONS INFORMATION PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS
