Datasheet LT3751 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | High Voltage Capacitor Charger Controller with Regulation |
| Pages / Page | 34 / 8 — PIN FUNCTIONS DONE (Pin 7/ Pin 5):. LVGATE (Pin 14/Pin 12):. CHARGE (Pin … |
| File Format / Size | PDF / 651 Kb |
| Document Language | English |
PIN FUNCTIONS DONE (Pin 7/ Pin 5):. LVGATE (Pin 14/Pin 12):. CHARGE (Pin 8/Pin 6):. HVGATE (Pin 15/Pin 13):
Model Line for this Datasheet
Text Version of Document
LT3751
PIN FUNCTIONS DONE (Pin 7/ Pin 5):
Open Collector Indication Pin. When
LVGATE (Pin 14/Pin 12):
Low Voltage Gate Pin. Connect the target output voltage (charge mode) is reached or the the NMOS gate terminal to this pin when operating VCC FAULT pin goes low, a transistor turns on. This pin needs below 8V. The internal gate driver will drive the voltage to a proper pull-up resistor or current source. the VCC rail. When operating VCC higher than 8V, tie this
CHARGE (Pin 8/Pin 6):
Charge Pin. Initiates a new charge pin directly to VCC. cycle (charge mode) or enables the part (regulation mode)
HVGATE (Pin 15/Pin 13):
High Voltage Gate Pin. Connect when driven higher than 1.5V. Bring this pin below 0.3V NMOS gate terminal to this pin for all VCC operating volt- to discontinue charging and put the part into shutdown. ages. Internal gate driver will drive the voltage to within Turn-on ramp rates should be between 10ns to 10ms. VCC – 2V during each switch cycle. CHARGE pin should not be directly ramped with VCC or
RBG (Pin 16/Pin 14):
Bias Generation Pin. Generates LT3751 may not properly initialize. a bias current set by 0.98V/RBG. Select RBG to achieve
CLAMP (Pin 9/Pin 7):
Internal Clamp Voltage Selection desired resistance for RDCM, RVOUT, and RVTRANS. Pin. Tie this pin to VCC to activate the internal 5.6V gate
NC (Pins 17, 19/Pins 15, 18):
No Connection. driver clamp. Tie this pin to ground to activate the internal 10.5V gate driver clamp.
RVOUT (Pin 18/Pin 16):
Output Voltage Sense Pin. Develops a current proportional to the output capacitor
FB (Pin 10/Pin 8):
Feedback Regulation Pin. Use this pin voltage. Connect a resistor between this pin and the drain to achieve low noise voltage regulation. FB is internally of NMOS such that: regulated to 1.22V when a resistive divider is tied from this pin to the output. FB pin should not float. Tie FB pin ⎛RV ⎞ V OUT to either a resistor divider or ground. OUT = 0.98 • N • ⎜ ⎟ − VDIODE ⎝ RBG ⎠
CSN (Pin 11/Pin 9):
Negative Current Sense Pin. Senses when RV external NMOS source current. Connect to local R OUT is set equal to RVTRANS, otherwise: SENSE ground connection for proper Kelvin sensing. The current ⎡ RV ⎛ RV ⎞⎤ V OUT ⎢ + V OUT ⎜ − 1 limit is set by 106mV/R OUT = N • 0.98 • TRANS ⎟⎥ SENSE. R ⎣ BG ⎝RVTRANS ⎠⎦
CSP (Pin 12/Pin 10):
Positive Current Sense Pin. Senses − VDIODE NMOS source current. Connect the NMOS source terminal and the current sense resistor to this pin. The current where VDIODE = forward voltage drop of diode D1 (refer limit is fixed at 106mV/R to the Block Diagram). SENSE in charge mode. The cur- rent limit can be reduced to a minimum 11mV/RSENSE in
RDCM (Pin 20/Pin 17):
Discontinuous Mode Sense Pin. regulation mode. Senses when the external NMOS drain is equal to 20µA •
V
RDCM + VTRANS and initiates the next switch cycle. Place
CC (Pin 13/Pin 11):
Input Supply Pin. Must be locally bypassed with high grade (X5R or better) ceramic capaci- a resistor equal to 0.45 times the resistor on the RVTRANS tor. The minimum operating voltage for V pin between this pin and VDRAIN. CC is 4.75V.
GND (Pin 21/Pin 21):
Ground. Tie directly to local ground plane. 3751fd 8 For more information www.linear.com/LT3751 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS DONE (Pin 7/ Pin 5):
Open Collector Indication Pin. When
LVGATE (Pin 14/Pin 12):
Low Voltage Gate Pin. Connect the target output voltage (charge mode) is reached or the the NMOS gate terminal to this pin when operating VCC FAULT pin goes low, a transistor turns on. This pin needs below 8V. The internal gate driver will drive the voltage to a proper pull-up resistor or current source. the VCC rail. When operating VCC higher than 8V, tie this
CHARGE (Pin 8/Pin 6):
Charge Pin. Initiates a new charge pin directly to VCC. cycle (charge mode) or enables the part (regulation mode)
HVGATE (Pin 15/Pin 13):
High Voltage Gate Pin. Connect when driven higher than 1.5V. Bring this pin below 0.3V NMOS gate terminal to this pin for all VCC operating volt- to discontinue charging and put the part into shutdown. ages. Internal gate driver will drive the voltage to within Turn-on ramp rates should be between 10ns to 10ms. VCC – 2V during each switch cycle. CHARGE pin should not be directly ramped with VCC or
RBG (Pin 16/Pin 14):
Bias Generation Pin. Generates LT3751 may not properly initialize. a bias current set by 0.98V/RBG. Select RBG to achieve
CLAMP (Pin 9/Pin 7):
Internal Clamp Voltage Selection desired resistance for RDCM, RVOUT, and RVTRANS. Pin. Tie this pin to VCC to activate the internal 5.6V gate
NC (Pins 17, 19/Pins 15, 18):
No Connection. driver clamp. Tie this pin to ground to activate the internal 10.5V gate driver clamp.
RVOUT (Pin 18/Pin 16):
Output Voltage Sense Pin. Develops a current proportional to the output capacitor
FB (Pin 10/Pin 8):
Feedback Regulation Pin. Use this pin voltage. Connect a resistor between this pin and the drain to achieve low noise voltage regulation. FB is internally of NMOS such that: regulated to 1.22V when a resistive divider is tied from this pin to the output. FB pin should not float. Tie FB pin ⎛RV ⎞ V OUT to either a resistor divider or ground. OUT = 0.98 • N • ⎜ ⎟ − VDIODE ⎝ RBG ⎠
CSN (Pin 11/Pin 9):
Negative Current Sense Pin. Senses when RV external NMOS source current. Connect to local R OUT is set equal to RVTRANS, otherwise: SENSE ground connection for proper Kelvin sensing. The current ⎡ RV ⎛ RV ⎞⎤ V OUT ⎢ + V OUT ⎜ − 1 limit is set by 106mV/R OUT = N • 0.98 • TRANS ⎟⎥ SENSE. R ⎣ BG ⎝RVTRANS ⎠⎦
CSP (Pin 12/Pin 10):
Positive Current Sense Pin. Senses − VDIODE NMOS source current. Connect the NMOS source terminal and the current sense resistor to this pin. The current where VDIODE = forward voltage drop of diode D1 (refer limit is fixed at 106mV/R to the Block Diagram). SENSE in charge mode. The cur- rent limit can be reduced to a minimum 11mV/RSENSE in
RDCM (Pin 20/Pin 17):
Discontinuous Mode Sense Pin. regulation mode. Senses when the external NMOS drain is equal to 20µA •
V
RDCM + VTRANS and initiates the next switch cycle. Place
CC (Pin 13/Pin 11):
Input Supply Pin. Must be locally bypassed with high grade (X5R or better) ceramic capaci- a resistor equal to 0.45 times the resistor on the RVTRANS tor. The minimum operating voltage for V pin between this pin and VDRAIN. CC is 4.75V.
GND (Pin 21/Pin 21):
Ground. Tie directly to local ground plane. 3751fd 8 For more information www.linear.com/LT3751 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
