Datasheet LTC3901 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Secondary Side Synchronous Driver for Push-Pull and Full-Bridge Converters |
| Pages / Page | 16 / 10 — APPLICATIO S I FOR ATIO. SYNC Input. Figure 9. VCC/PVCC Regulator. Figure … |
| File Format / Size | PDF / 239 Kb |
| Document Language | English |
APPLICATIO S I FOR ATIO. SYNC Input. Figure 9. VCC/PVCC Regulator. Figure 8. SYNC Input Circuit. VCC/PVCC Regulator
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LTC3901
U U W U APPLICATIO S I FOR ATIO
the resistors to the LTC3901 CSX+/CSX– pins as short as D3 MBR0540 possible . Add a series resistor, R T1 CSX3, with value equal to SECONDARY parallel sum of RCSX1 and RCSX2 to the CSX– pin and WINDING RZ connect the other end of R 0.1µF CSX3 directly to the source of the 2k RB OPTIONAL MOSFET. QREG FZT690B
SYNC Input
6V PVCC DZ VCC Figure 8 shows the external circuit for the LTC3901 SYNC CPVCC RVCC CVCC 4.7 100Ω input. The gate drive transformer (T2) should be selected µF 1µF based on the primary switching frequency and SDRA/ 3901 F09 SDRB output voltage.
Figure 9. VCC/PVCC Regulator
The values of the CSG and RSYNC should then be adjusted to obtain a optimum SYNC pulse shape and amplitude. The higher than 4.5V. This reduces the number of external amplitude of the SYNC pulse should be much higher than components needed. the LTC3901 SYNC threshold of ±1.4V. Amplitudes greater The LTC3901 has an UVLO detector that pulls the drivers’ than ±5V will help to speed up the SYNC comparator and output low if VCC < 4.1V. The output remains off from reduce the propagation delay from SYNC to the drivers. VCC = 1V to 4.1V. The UVLO detector has 0.5V of hyster- When SDRA and SDRB lines go low, the resulting under- esis to prevent chattering. shoot or overshoot must not exceed the minimum SYNC In a typical push-pull converter, the secondary side cir- threshold of ±1V. cuits have no power until the primary side controller starts CSG operating. Since power for the LTC3901 is derived from 0.1µF T2 the power transformer T1, the LTC3901 will initially re- LTC3901 SDRB SYNC PRIMARY main off. During this period (VCC < 4.1V), the synchronous R CONTROLLER SYNC 4.7k MOSFETs ME and MF will remain off and the MOSFETs’ SDRA RSG body diodes will conduct. The MOSFETs may experience 220Ω 3901 F08 very high power dissipation due to a high voltage drop in the body diodes. To prevent MOSFET damage, a V
Figure 8. SYNC Input Circuit
CC voltage greater than 4.1V should be provided quickly. The VCC supply circuit in Figure 9 will provide power for the
VCC/PVCC Regulator
LTC3901 within the first few switching pulses of the The VCC/PVCC supply for the LTC3901 can be generated by primary controller, preventing overheating of the MOSFETs. peak rectifying the transformer secondary winding as shown in Figure 9. The Zener diode DZ sets the output
Full-Bridge Converter Application
voltage (VZ – 0.7V). Resistor RB (on the order of a few The LTC3901 can be used in full-bridge converter applica- hundred ohms), in series with the base of QREG, may be tions. Figure 10 shows a simplified full-bridge converter required to surpress high frequency oscillations depend- circuit. The LTC3901 circuit and operation is the same as ing on QREG’s selection. A power MOSFET can also be used in the push-pull application (refer to Figure 1). On the pri- by increasing the zener diode value to offset the drop of the mary side there are four power MOSFETs, MA to MD, driven gate-to-source voltage. The VCC input is separated from by the respective outputs of the primary controller. Trans- the PVCC input through a 100Ω resistor. This lowers the former T3 and T4 step up the gate drives for MA and MC. driver switching feedthrough. Connect a 1µF bypass ca- pacitor for the VCC supply. PVCC supply current varies Each full cycle of the full-bridge converter includes four linearly with the supply voltage, driver load and clock distinct periods which are similar to those found in the frequency. A 4.7µF bypass capacitor for the PVCC supply push-pull application. Figure 11 shows the full-bridge is sufficient for most applications. Alternatively, the converter switching waveforms. The shaded areas corre- LTC3901 can be powered directly by VOUT if the voltage is spond to power delivery periods. 3901f 10
U U W U APPLICATIO S I FOR ATIO
the resistors to the LTC3901 CSX+/CSX– pins as short as D3 MBR0540 possible . Add a series resistor, R T1 CSX3, with value equal to SECONDARY parallel sum of RCSX1 and RCSX2 to the CSX– pin and WINDING RZ connect the other end of R 0.1µF CSX3 directly to the source of the 2k RB OPTIONAL MOSFET. QREG FZT690B
SYNC Input
6V PVCC DZ VCC Figure 8 shows the external circuit for the LTC3901 SYNC CPVCC RVCC CVCC 4.7 100Ω input. The gate drive transformer (T2) should be selected µF 1µF based on the primary switching frequency and SDRA/ 3901 F09 SDRB output voltage.
Figure 9. VCC/PVCC Regulator
The values of the CSG and RSYNC should then be adjusted to obtain a optimum SYNC pulse shape and amplitude. The higher than 4.5V. This reduces the number of external amplitude of the SYNC pulse should be much higher than components needed. the LTC3901 SYNC threshold of ±1.4V. Amplitudes greater The LTC3901 has an UVLO detector that pulls the drivers’ than ±5V will help to speed up the SYNC comparator and output low if VCC < 4.1V. The output remains off from reduce the propagation delay from SYNC to the drivers. VCC = 1V to 4.1V. The UVLO detector has 0.5V of hyster- When SDRA and SDRB lines go low, the resulting under- esis to prevent chattering. shoot or overshoot must not exceed the minimum SYNC In a typical push-pull converter, the secondary side cir- threshold of ±1V. cuits have no power until the primary side controller starts CSG operating. Since power for the LTC3901 is derived from 0.1µF T2 the power transformer T1, the LTC3901 will initially re- LTC3901 SDRB SYNC PRIMARY main off. During this period (VCC < 4.1V), the synchronous R CONTROLLER SYNC 4.7k MOSFETs ME and MF will remain off and the MOSFETs’ SDRA RSG body diodes will conduct. The MOSFETs may experience 220Ω 3901 F08 very high power dissipation due to a high voltage drop in the body diodes. To prevent MOSFET damage, a V
Figure 8. SYNC Input Circuit
CC voltage greater than 4.1V should be provided quickly. The VCC supply circuit in Figure 9 will provide power for the
VCC/PVCC Regulator
LTC3901 within the first few switching pulses of the The VCC/PVCC supply for the LTC3901 can be generated by primary controller, preventing overheating of the MOSFETs. peak rectifying the transformer secondary winding as shown in Figure 9. The Zener diode DZ sets the output
Full-Bridge Converter Application
voltage (VZ – 0.7V). Resistor RB (on the order of a few The LTC3901 can be used in full-bridge converter applica- hundred ohms), in series with the base of QREG, may be tions. Figure 10 shows a simplified full-bridge converter required to surpress high frequency oscillations depend- circuit. The LTC3901 circuit and operation is the same as ing on QREG’s selection. A power MOSFET can also be used in the push-pull application (refer to Figure 1). On the pri- by increasing the zener diode value to offset the drop of the mary side there are four power MOSFETs, MA to MD, driven gate-to-source voltage. The VCC input is separated from by the respective outputs of the primary controller. Trans- the PVCC input through a 100Ω resistor. This lowers the former T3 and T4 step up the gate drives for MA and MC. driver switching feedthrough. Connect a 1µF bypass ca- pacitor for the VCC supply. PVCC supply current varies Each full cycle of the full-bridge converter includes four linearly with the supply voltage, driver load and clock distinct periods which are similar to those found in the frequency. A 4.7µF bypass capacitor for the PVCC supply push-pull application. Figure 11 shows the full-bridge is sufficient for most applications. Alternatively, the converter switching waveforms. The shaded areas corre- LTC3901 can be powered directly by VOUT if the voltage is spond to power delivery periods. 3901f 10
