Datasheet AT90S4433, AT90LS4433 (Atmel) - 5
| Manufacturer | Atmel |
| Description | 8-bit AVR Microcontroller with 4K Bytes of In-System Programmable Flash. Not Recommend for New Designs. Use ATmega8 |
| Pages / Page | 126 / 5 — AT90S/LS4433. Pin Descriptions. VCC. GND. Port B (PB5..PB0). Port C … |
| File Format / Size | PDF / 1.5 Mb |
| Document Language | English |
AT90S/LS4433. Pin Descriptions. VCC. GND. Port B (PB5..PB0). Port C (PC5..PC0). Port D (PD7..PD0). RESET. XTAL1. XTAL2. AVCC. AREF. AGND
Model Line for this Datasheet
Text Version of Document
link to page 73 link to page 81 link to page 64
AT90S/LS4433 Pin Descriptions VCC
Supply voltage.
GND
Ground.
Port B (PB5..PB0)
Port B is a 6-bit bi-directional I/O port with internal pull-up resistors. The Port B output buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. Port B also serves the functions of various special features of the AT90S4433 as listed on page 73. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Port C (PC5..PC0)
Port C is a 6-bit bi-directional I/O port with internal pull-up resistors. The Port C output buffers can sink 20 mA. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. Port C also serves as the analog inputs to the A/D Converter. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. Port D also serves the functions of various special features of the AT90S4433 as listed on page 81. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.
RESET
Reset input. An External Reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit
XTAL2
Output from the inverting oscillator amplifier
AVCC
AVCC is the supply voltage for Port A and the A/D Converter. If the ADC is not used, this pin must be connected to V . If the ADC is used, this pin should be connected to CC V via a low-pass filter. See page 64 for details on operation of the ADC. CC
AREF
AREF is the analog reference input for the A/D Converter. For ADC operations, a volt- age in the range 2.0V to AVCC must be applied to this pin.
AGND
If the board has a separate analog ground plane, this pin should be connected to this ground plane. Otherwise, connect to GND.
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1042H–AVR–04/03 Document Outline Features Pin Configurations Description Block Diagram Pin Descriptions VCC GND Port B (PB5..PB0) Port C (PC5..PC0) Port D (PD7..PD0) RESET XTAL1 XTAL2 AVCC AREF AGND Clock Options Crystal Oscillator External Clock Architectural Overview General Purpose Register File X-register, Y-register and Z- register ALU – Arithmetic Logic Unit In-System Programmable Flash Program Memory SRAM Data Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Direct, Two Registers Rd and Rr I/O Direct Data Direct Data Indirect with Displacement Data Indirect Data Indirect with Pre- decrement Data Indirect with Post- increment Constant Addressing Using the LPM Instruction Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL EEPROM Data Memory Memory Access Times and Instruction Execution Timing I/O Memory Status Register – SREG Stack Pointer – SP Reset and Interrupt Handling Reset Sources Power-on Reset External Reset Brown-out Detection Watchdog Reset MCU Status Register – MCUSR Interrupt Handling General Interrupt Mask Register – GIMSK General Interrupt Flag Register – GIFR Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR External Interrupts Interrupt Response Time MCU Control Register – MCUCR Sleep Modes Idle Mode Power-down Mode Timer/Counters Timer/Counter Prescaler 8-bit Timer/Counter0 Timer/Counter0 Control Register – TCCR0 Timer Counter0 – TCNT0 16-bit Timer/Counter1 Timer/Counter1 Control Register A – TCCR1A Timer/Counter1 Control Register B – TCCR1B Timer/Counter1 – TCNT1H and TCNT1L Timer/Counter1 Output Compare Register – OCR1H and OCR1L Timer/Counter1 Input Capture Register – ICR1H and ICR1L Timer/Counter1 in PWM Mode Watchdog Timer Watchdog Timer Control Register – WDTCR EEPROM Read/Write Access EEPROM Address Register – EEAR EEPROM Data Register – EEDR EEPROM Control Register – EECR Prevent EEPROM Corruption Serial Peripheral Interface – SPI SS Pin Functionality Data Modes SPI Control Register – SPCR SPI Status Register – SPSR SPI Data Register – SPDR UART Data Transmission Data Reception Multi-processor Communication Mode UART Control UART I/O Data Register – UDR UART Control and Status Register A – UCSRA UART Control and Status Register B – UCSRB Baud Rate Generator UART Baud Rate Register – UBRR Analog Comparator Analog Comparator Control and Status Register – ACSR Analog-to-Digital Converter Features Operation Prescaling ADC Noise Canceler Function ADC Multiplexer Select Register – ADMUX ADC Control and Status Register – ADCSR ADC Data Register – ADCL AND ADCH Scanning Multiple Channels ADC Noise Canceling Techniques ADC Characteristics TA = -40°C to 85°C I/O Ports Port B Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB Port B as General Digital I/O Alternate Functions of Port B Port C Port C Data Register – PORTC Port C Data Direction Register – DDRC Port C Input Pins Address – PINC Port C as General Digital I/O Port C Schematics Port D Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Port D as General Digital I/O Alternate Functions of Port D Port D Schematics Memory Programming Program and Data Memory Lock Bits Fuse Bits Signature Bytes Programming the Flash and EEPROM Parallel Programming Signal Names Enter Programming Mode Chip Erase Programming the Flash Reading the Flash Programming the EEPROM Reading the EEPROM Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Parallel Programming Characteristics Serial Downloading Serial Programming Algorithm Data Polling EEPROM Data Polling Flash Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings* DC Characteristics External Clock Drive Waveforms Typical Characteristics Register Summary Instruction Set Summary Ordering Information Packaging Information 32A 28P3 Errata for AT90S/LS4433 Rev. Rev. C/D/E/F Data Sheet ChangeLog for AT90S/LS4433 Changes from Rev. 1042E-09/01 to Ref. 1042F-03/02 Changes from Rev. 1042F-03/02 to Ref. 1042G-09/02 Changes from Rev. 1042G-09/02 to Ref. 1042H-04/03 Table of Contents
AT90S/LS4433 Pin Descriptions VCC
Supply voltage.
GND
Ground.
Port B (PB5..PB0)
Port B is a 6-bit bi-directional I/O port with internal pull-up resistors. The Port B output buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. Port B also serves the functions of various special features of the AT90S4433 as listed on page 73. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Port C (PC5..PC0)
Port C is a 6-bit bi-directional I/O port with internal pull-up resistors. The Port C output buffers can sink 20 mA. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. Port C also serves as the analog inputs to the A/D Converter. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. Port D also serves the functions of various special features of the AT90S4433 as listed on page 81. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.
RESET
Reset input. An External Reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit
XTAL2
Output from the inverting oscillator amplifier
AVCC
AVCC is the supply voltage for Port A and the A/D Converter. If the ADC is not used, this pin must be connected to V . If the ADC is used, this pin should be connected to CC V via a low-pass filter. See page 64 for details on operation of the ADC. CC
AREF
AREF is the analog reference input for the A/D Converter. For ADC operations, a volt- age in the range 2.0V to AVCC must be applied to this pin.
AGND
If the board has a separate analog ground plane, this pin should be connected to this ground plane. Otherwise, connect to GND.
5
1042H–AVR–04/03 Document Outline Features Pin Configurations Description Block Diagram Pin Descriptions VCC GND Port B (PB5..PB0) Port C (PC5..PC0) Port D (PD7..PD0) RESET XTAL1 XTAL2 AVCC AREF AGND Clock Options Crystal Oscillator External Clock Architectural Overview General Purpose Register File X-register, Y-register and Z- register ALU – Arithmetic Logic Unit In-System Programmable Flash Program Memory SRAM Data Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Direct, Two Registers Rd and Rr I/O Direct Data Direct Data Indirect with Displacement Data Indirect Data Indirect with Pre- decrement Data Indirect with Post- increment Constant Addressing Using the LPM Instruction Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL EEPROM Data Memory Memory Access Times and Instruction Execution Timing I/O Memory Status Register – SREG Stack Pointer – SP Reset and Interrupt Handling Reset Sources Power-on Reset External Reset Brown-out Detection Watchdog Reset MCU Status Register – MCUSR Interrupt Handling General Interrupt Mask Register – GIMSK General Interrupt Flag Register – GIFR Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR External Interrupts Interrupt Response Time MCU Control Register – MCUCR Sleep Modes Idle Mode Power-down Mode Timer/Counters Timer/Counter Prescaler 8-bit Timer/Counter0 Timer/Counter0 Control Register – TCCR0 Timer Counter0 – TCNT0 16-bit Timer/Counter1 Timer/Counter1 Control Register A – TCCR1A Timer/Counter1 Control Register B – TCCR1B Timer/Counter1 – TCNT1H and TCNT1L Timer/Counter1 Output Compare Register – OCR1H and OCR1L Timer/Counter1 Input Capture Register – ICR1H and ICR1L Timer/Counter1 in PWM Mode Watchdog Timer Watchdog Timer Control Register – WDTCR EEPROM Read/Write Access EEPROM Address Register – EEAR EEPROM Data Register – EEDR EEPROM Control Register – EECR Prevent EEPROM Corruption Serial Peripheral Interface – SPI SS Pin Functionality Data Modes SPI Control Register – SPCR SPI Status Register – SPSR SPI Data Register – SPDR UART Data Transmission Data Reception Multi-processor Communication Mode UART Control UART I/O Data Register – UDR UART Control and Status Register A – UCSRA UART Control and Status Register B – UCSRB Baud Rate Generator UART Baud Rate Register – UBRR Analog Comparator Analog Comparator Control and Status Register – ACSR Analog-to-Digital Converter Features Operation Prescaling ADC Noise Canceler Function ADC Multiplexer Select Register – ADMUX ADC Control and Status Register – ADCSR ADC Data Register – ADCL AND ADCH Scanning Multiple Channels ADC Noise Canceling Techniques ADC Characteristics TA = -40°C to 85°C I/O Ports Port B Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB Port B as General Digital I/O Alternate Functions of Port B Port C Port C Data Register – PORTC Port C Data Direction Register – DDRC Port C Input Pins Address – PINC Port C as General Digital I/O Port C Schematics Port D Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Port D as General Digital I/O Alternate Functions of Port D Port D Schematics Memory Programming Program and Data Memory Lock Bits Fuse Bits Signature Bytes Programming the Flash and EEPROM Parallel Programming Signal Names Enter Programming Mode Chip Erase Programming the Flash Reading the Flash Programming the EEPROM Reading the EEPROM Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes Parallel Programming Characteristics Serial Downloading Serial Programming Algorithm Data Polling EEPROM Data Polling Flash Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings* DC Characteristics External Clock Drive Waveforms Typical Characteristics Register Summary Instruction Set Summary Ordering Information Packaging Information 32A 28P3 Errata for AT90S/LS4433 Rev. Rev. C/D/E/F Data Sheet ChangeLog for AT90S/LS4433 Changes from Rev. 1042E-09/01 to Ref. 1042F-03/02 Changes from Rev. 1042F-03/02 to Ref. 1042G-09/02 Changes from Rev. 1042G-09/02 to Ref. 1042H-04/03 Table of Contents
