Datasheet AT90S2333, AT90LS2333, AT90S4433, AT90LS4433 - Preliminary (Atmel) - 3
| Manufacturer | Atmel |
| Description | 8-bit AVR Microcontroller with 2K/4K bytes In-System Programmable Flash |
| Pages / Page | 13 / 3 — AT90S/LS2333 and AT90S/LS4433. Block Diagram. Figure 1 |
| File Format / Size | PDF / 320 Kb |
| Document Language | English |
AT90S/LS2333 and AT90S/LS4433. Block Diagram. Figure 1
Model Line for this Datasheet
Text Version of Document
AT90S/LS2333 and AT90S/LS4433 Block Diagram Figure 1.
The AT90S2333/4433 Block Diagram PC0 - PC5 VCC PORTC DRIVERS GND DATA REGISTER DATA DIR. PORTC REG. PORTC 8-BIT DATA BUS AVCC ANALOG MUX ADC AGND XTAL1 AREF INTERNAL OSCILLATOR OSCILLATOR XTAL2 PROGRAM STACK WATCHDOG TIMING AND RESET COUNTER POINTER TIMER CONTROL PROGRAM MCU CONTROL SRAM FLASH REGISTER INSTRUCTION GENERAL TIMER/ REGISTER PURPOSE COUNTERS REGISTERS X INSTRUCTION Y INTERRUPT DECODER Z UNIT CONTROL ALU EEPROM LINES STATUS REGISTER PROGRAMMING SPI UART LOGIC DATA REGISTER DATA DIR. DATA REGISTER DATA DIR. PORTB REG. PORTB PORTD REG. PORTD - + ANALOG COMPARATOR PORTB DRIVERS PORTD DRIVERS PB0 - PB5 PD0 - PD7
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Document Outline Features Description Block Diagram Pin Descriptions VCC GND Port B (PB5..PB0) Port C (PC5..PC0) Port D (PD7..PD0) RESET XTAL1 XTAL2 AVCC AREF AGND Architectural Overview Register Summary (Continued) Instruction Set Summary (Continued) Ordering Information Pin Configurations
The AT90S2333/4433 Block Diagram PC0 - PC5 VCC PORTC DRIVERS GND DATA REGISTER DATA DIR. PORTC REG. PORTC 8-BIT DATA BUS AVCC ANALOG MUX ADC AGND XTAL1 AREF INTERNAL OSCILLATOR OSCILLATOR XTAL2 PROGRAM STACK WATCHDOG TIMING AND RESET COUNTER POINTER TIMER CONTROL PROGRAM MCU CONTROL SRAM FLASH REGISTER INSTRUCTION GENERAL TIMER/ REGISTER PURPOSE COUNTERS REGISTERS X INSTRUCTION Y INTERRUPT DECODER Z UNIT CONTROL ALU EEPROM LINES STATUS REGISTER PROGRAMMING SPI UART LOGIC DATA REGISTER DATA DIR. DATA REGISTER DATA DIR. PORTB REG. PORTB PORTD REG. PORTD - + ANALOG COMPARATOR PORTB DRIVERS PORTD DRIVERS PB0 - PB5 PD0 - PD7
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Document Outline Features Description Block Diagram Pin Descriptions VCC GND Port B (PB5..PB0) Port C (PC5..PC0) Port D (PD7..PD0) RESET XTAL1 XTAL2 AVCC AREF AGND Architectural Overview Register Summary (Continued) Instruction Set Summary (Continued) Ordering Information Pin Configurations
