Datasheet LTC4121, LTC4121-4.2 (Analog Devices) - 5

LTC4121/LTC4121-4.2
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = VRUN = 15V, VCHGSNS = VBAT = 4V, RPROG = 3.01k, VFB = 2.29V (LTC4121), VBATSNS = 4V (LTC4121-4.2). Current into a pin is positive out of a pin is negative. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS RUN
VEN Enable Threshold VRUN Rising l 2.35 2.45 2.55 V Hysteresis VRUN Falling 200 mV Run Pin Input Current VRUN = 40V 0.01 0.1 µA VSD Shutdown Threshold VRUN Falling l 0.4 1.2 V Hysteresis 220 mV
FREQ
FREQ Pin Input Low l 0.4 V FREQ Pin Input High l 3.6 V FREQ Pin Input Current 0 < VFREQ < VINTVCC ±1 µA
MPPT
IMPPT MPPT Pin Leakage Current VMPPT = 4.2V l 15 1000 nA TMP MPPT Sample Period Period Between Charger Disabled Events 28 s PWMP MPPT Sample Pulse Width Charger Disabled Pulse Width 36 ms KF Internal Divider Gain Internal DAC Voltage as a Ratio to VIN 0.098 0.1 0.102 V/V VMP(OS) MPPT Error Amp Gain Offset VMPPT – VDAC, IBAT = 50%• ICHG 10 –45 –100 mV
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 4:
Standby mode occurs when the LTC4121/LTC4121-4.2 stops may cause permanent damage to the device. Exposure to any Absolute switching due to an NTC fault, MPPT pause, or when the charge current Maximum Rating condition for extended periods may affect device has dropped low enough to enter Burst Mode operation. Disabled mode reliability and lifetime. occurs when VRUN is between VSD and VEN. Shutdown mode occurs
Note 2:
The LTC4121 is tested under pulsed load conditions such that when VRUN is below VSD or when the differential undervoltage lockout T is engaged. Sleep mode occurs after a timeout while the battery voltage J ≈ TA. The LTC4121E is guaranteed to meet performance specifications for junction temperatures from 0°C to 85°C. Specifications over the remains above the VRCHG or VRCHG_42 threshold. –40°C to 125°C operating junction temperature range are assured by
Note 5:
The internal supply INTVCC should only be used for the NTC design, characterization and correlation with statistical process controls. divider, it should not be used for any other loads The LTC4121I is guaranteed over the full –40°C to 125°C operating
Note 6:
For the LTC4121, the FB pin is measured with a resistance of 588k junction temperature range. Note that the maximum ambient temperature in series with the pin. consistent with these specifications is determined by specific operating
Note 7:
h conditions in conjunction with board layout, the rated package thermal C/10 is expressed as a fraction of measured full charge current as measured at the PROG pin voltage when the CHRG pin de-asserts. impedance, and other environmental factors.
Note 8:
In an application circuit with an inductor connected from SW to
Note 3:
If a battery voltage greater than 11V can be hot plugged to the CHGSNS, the total battery leakage current when disabled is the sum of LTC4121 a reverse blocking diode is required in series with the BAT pin to I prevent large inrush current into the low impedance BAT pin. BATSNS and ISW (LTC4121-4.2) or IBAT and IFBG_LEAK and ISW (LTC4121).
Note 9:
When no supply is present at IN, the SW powers IN through the body diode of the top side switch. This may cause additional SW pin current depending on the load present at IN.
Note 10:
Guaranteed by design and/or correlation to static test. 4121fc For more information www.linear.com/LTC4121 5 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Applications Examples Package Description Typical Application Related Parts