Datasheet LTC4110 (Analog Devices) - 8

LTC4110
PIN FUNCTIONS DCIN (Pin 1):
External DC Power Sense Input. Provides a smart battery or Li-Ion battery is in any phase of charging control input and supply for the main supply ideal diode or when lead acid battery charge current is >C/x where: function. C x = • 5
CLN (Pin 2):
Current Limit Sense Negative Input. See I CHG CLP pin. (See C/x Charge Termination section for more details).
CLP (Pin 3):
Current Limit Sense Positive Input. This pin If the No SMBus option is selected with the SELA pin, and the CLN pin form a differential input that senses volt- the GPIO1 pin defaults as battery charge status. Refer age on an external resistor for reverse current entering the to Table 5a. power source while in low loss calibration mode. Should the current approach reversal, this function will terminate
GPIO2 (Pin 10):
General Purpose I/O Pin. A logic-level I/O bit calibration. An RC fi lter may be required to fi lter out system port that is confi gurable as a host-driven input/output port load noise. Connect both CLP and CLN pins to GND to or as a battery undervoltage status output (BKUP_FLTb) disable this function. A differential voltage of >1V between with an open-drain N-MOSFET that is asserted low only the CLP and CLN pins may damage the device. while in backup mode if the battery’s average cell voltage drops below voltage programmed by the VDIS pin. If the
ACPDLY (Pin 4):
ACPb Delay Control Pin. A capacitor No SMBus option is selected with the SELA pin, then the connected from ACPDLY to GND and a resistor from GPIO2 pin defaults as battery undervoltage status. Refer VREF to GND programs delay in the ACPb pin high-to-low to Table 5c. transition. Open if minimum delay is desired.
GPIO3 (Pin 11):
General Purpose I/O Pin. A logic-level I/O
DCDIV (Pin 5):
AC Present Detection Input. Backup bit port that is confi gurable as a host-driven input/output operation is invoked when the system power voltage, port or as a calibration complete status output (CAL_COM- divided by an external resistor divider, falls below the PLETEb) with an open-drain N-MOSFET that is asserted threshold of this pin. low when calibration has been completed. If the SELA pin
SHDN (Pin 6):
Active High Shutdown/Reset Control Logic is programmed for no SMBus use then the status output Input. Forces micropower shutdown mode if high when is charge fault (CHGFLTb) instead of calibration complete. DCIN supply is removed. Forces all registers to reset if high Refer to Table 5e. when DCIN supply is present. Normally tied to ground.
SELA (Pin 12):
SMBus Address Selection Input. Selects Internal pin pull-up current. the LTC4110 SMBus address to facilitate redundant backup
SDA (Pin 7):
SMBus Bidirectional Data Signal. Connect systems when standard batteries are used. Connect to to V GND for 12h, V DD when not in use. DD for 28h and the VREF pin for 20h. When a smart battery is selected by the TYPE pin, the SELA pin
SCL (Pin 8):
SMBus Clock Signal Input From SMBus Host. must be connected to GND to select address 12h. If the Connect to VDD when not in use. SMBus is not used or to force all GPIOs to status mode
GPIO1 (Pin 9):
General Purpose I/O or Charge Status Pin. A upon power-up, connect pin to a typically 0.5 • VREF volt- logic-level I/O bit port that is confi gurable as a host-driven age from VREF pin resistor divider. The SMBus address, input/output port or as a battery charge status output (CHGb) if used, will be 12h. with an open-drain N-MOSFET that is asserted low when any 4110fb 8