Datasheet ADE9153A (Analog Devices) - 5

ManufacturerAnalog Devices
DescriptionEnergy Metering IC with Autocalibration
Pages / Page50 / 5 — Data Sheet. ADE9153A. Parameter. Min. Typ. Max. Unit. Test …
File Format / SizePDF / 510 Kb
Document LanguageEnglish

Data Sheet. ADE9153A. Parameter. Min. Typ. Max. Unit. Test Conditions/Comments

Data Sheet ADE9153A Parameter Min Typ Max Unit Test Conditions/Comments

Model Line for this Datasheet

Text Version of Document

link to page 19 link to page 19
Data Sheet ADE9153A Parameter Min Typ Max Unit Test Conditions/Comments
Channel Drift (PGA, ADC, Internal See the Terminology section Voltage Reference) Current Channel A ±5 ±30 ppm/°C Current Channel B ±20 ±50 ppm/°C Voltage Channel ±20 ±50 ppm/°C Differential Input Impedance (DC) See the Terminology section Current Channel A 5000 7800 kΩ Current Channel B 100 113 kΩ Voltage Channel 240 256 kΩ INTERNAL VOLTAGE REFERENCE Nominal = 1.25 V ± 1 mV Voltage Reference 1.25 V TA = 25°C at REFIN Temperature Coefficient ±5 ±30 ppm/°C TA = −40°C to +85°C; tested during device characterization TEMPERATURE SENSOR Temperature Accuracy ±5 °C −40°C to +85°C Temperature Readout Step Size 0.3 °C CRYSTAL OSCILLATOR All specifications at CLKIN = 12.288 MHz; the crystal oscillator is designed to interface with 100 μW crystals Input Clock Frequency 12.287 12.288 12.289 MHz ±100 ppm Internal Capacitance on CLKIN, 4 pF CLKOUT Internal Feedback Resistance 2.58 MΩ Between CLKIN and CLKOUT Transconductance (gm) 5 8.7 mA/V EXTERNAL CLOCK INPUT Input Clock Frequency, CLKIN 12.287 12.288 12.289 MHz ±100 ppm Duty Cycle 45:55 50:50 55:45 CLKIN Logic Input Voltage 3.3 V tolerant High, VINH 1.2 V Low, VINL 0.5 V LOGIC INPUTS—MOSI/RX, SCLK Input Voltage High, VINH 2.4 V Low, VINL 0.8 V Input Current, IIN 11 μA VIN = 0 V Input Capacitance, CIN 10 pF LOGIC OUTPUTS MISO/TX, IRQ Output Voltage High, VOH 2.5 V ISOURCE = 4 mA Low, VOL 0.4 V ISINK = 3 mA Internal Capacitance, CIN 10 pF CF1, CF2 Output Voltage High, VOH 2.4 V ISOURCE = 6 mA Low, VOL 0.8 V ISINK = 6 mA Internal Capacitance, CIN 10 pF LOW DROPOUT REGULATORS (LDOs) AVDD 1.9 V DVDD 1.7 V VDD2P5 2.5 V Rev. 0 | Page 5 of 50 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATIONS CIRCUIT TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AUTOCALIBRATION SPI TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS ENERGY LINEARITY OVER SUPPLY AND TEMPERATURE ENERGY ERROR OVER FREQUENCY AND POWER FACTOR RMS LINEARITY OVER TEMPERATURE AND RMS ERROR OVER FREQUENCY SIGNAL-TO-NOISE RATIO (SNR) PERFORMANCE OVER DYNAMIC RANGE TEST CIRCUIT TERMINOLOGY THEORY OF OPERATION mSURE AUTOCALIBRATION FEATURE mSure System Warning Interrupts MEASUREMENTS Current Channel Current Channel Gain, xIGAIN High-Pass Filter Digital Integrator Phase Compensation Voltage Channel RMS and Power Measurements Total RMS Total Active Power Fundamental Reactive Power Total Apparent Power Energy Accumulation, Power Accumulation, and No Load Detection Features Energy Accumulation Energy Accumulation Modes Reset Energy Register on Read Power Accumulation No Load Detection Feature Digital to Frequency Conversion—CFx Output Calibration Frequency (CF) Energy Selection Configuring the CFx Pulse Width CFx Pulse Sign Clearing the CFx Accumulator POWER QUALITY MEASUREMENTS Zero-Crossing Detection CF1/ZX/DREADY Zero-Crossing Timeout Line Period Calculation Angle Measurement One Cycle RMS Measurement Dip and Swell Indication Overcurrent Indication Peak Detection Power Factor Temperature APPLICATIONS INFORMATION INTERRUPTS/EVENTS PIN INTERRUPTS SERVICING INTERRUPTS CF2/ZX/DREADY EVENT PIN ACCESSING ON-CHIP DATA SPI PROTOCOL OVERVIEW UART INTERFACE COMMUNICATION VERIFICATION REGISTERS CRC OF CONFIGURATION REGISTERS CONFIGURATION LOCK REGISTER INFORMATION REGISTER SUMMARY REGISTER DETAILS OUTLINE DIMENSIONS ORDERING GUIDE