Datasheet LTC1152 (Analog Devices) - 6

ManufacturerAnalog Devices
DescriptionRail-to-Rail Input Rail-to-Rail Output Zero-Drift Op Amp
Pages / Page8 / 6 — APPLICATI. S I FOR ATIO. Rail-to-Rail Operation. Figure 1. LTC1152 …
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APPLICATI. S I FOR ATIO. Rail-to-Rail Operation. Figure 1. LTC1152 Internal Block Diagram. Output Drive. Internal Charge Pump

APPLICATI S I FOR ATIO Rail-to-Rail Operation Figure 1 LTC1152 Internal Block Diagram Output Drive Internal Charge Pump

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LTC1152
O U U W U APPLICATI S I FOR ATIO Rail-to-Rail Operation
VCC (PIN 7) The LTC1152 is a rail-to-rail input common-mode range, VCC + 2V INTERNAL CP (PIN 8) CHARGE rail-to-rail output swing op amp. Most CMOS op amps, PUMP 0.1µF* including the entire LTC zero-drift amplifier line, and even – a few bipolar op amps, can and do, claim rail-to-rail output –IN swing. One obvious use for such a device is to provide a OUTPUT INPUT OUT + RAIL TO RAIL unity-gain buffer for 0V to 5V signals running from a single +IN 5V power supply. This is not possible with the vast *OPTIONAL EXTERNAL majority of so-called “rail-to-rail” op amps; although the CAPACITOR TO REDUCE CHARGE PUMP FEEDTHROUGH 1152 F01 output can swing to both rails, the negative input (which is connected to the output) will exceed the common-mode
Figure 1. LTC1152 Internal Block Diagram
input range of the device at some point (generally about 1.5V below the positive supply), opening the feedback time. This diode can stand short-term peak currents of loop and causing unpredictable and sometimes bizarre about 50mA, allowing it to quickly charge external capaci- behavior. tance to ground or V –. Large capacitors (>1µF) should not The LTC1152 is an exception to this rule. It features both be connected between pin 8 and ground or V – to prevent rail-to-rail output swing and rail-to-rail input common- excessive diode current from flowing at start-up. The mode range (CMR); the input CMR actually extends be- LTC1152 can withstand continuous short circuits be- yond either rail by about 0.3V. This allows unity-gain tween pin 8 and V +; however, short circuiting pin 8 to buffer circuits to operate with any input signal within the ground or V – will cause large amounts of current to flow power supply rails; input signal swing is limited only by the through the diode, destroying the LTC1152. Don’t do it. output stage swing into the load. Additionally, signals occurring at either rail (power supply current sensing, for
Output Drive
example) can be amplified without any special circuitry. The LTC1152 features an enhanced output stage that can sink and source 10mA with a single 5V supply while
Internal Charge Pump
maintaining rail-to-rail output swing under most loading The LTC1152 achieves its rail-to-rail input CMR by using conditions. The output stage can be modeled as a perfect a charge pump to generate an internal voltage approxi- rail-to-rail voltage source with a resistor in series with it; mately 2V higher than V+. The input stages of the op amp this open-loop output resistance limits the output swing are run from this higher voltage, making signals at V+ by creating a resistor divider with the output load. appear to be 2V below the front end’s power supply (Figure The output resistance drops as total power supply voltage 1). The charge pump is contained entirely within the increases, as shown in the typical performance curves. It LTC1152; no external components are required. is typically 140Ω with a single 5V supply, allowing a 4.4V About 100µVP-P of residual charge pump switching noise output swing into a 1k resistor with a single 5V supply. will be present on the output of the LTC1152. This feedthrough is at 4.7MHz, higher than the gain-bandwidth VCC (PIN 7) of the LTC1152, and will generally not cause any prob- lems. Very sensitive applications can reduce this LTC1152 ROUT OUTPUT OUT (PIN 6) feedthrough by connecting a capacitor from the CP pin DRIVER ≈140Ω AT 5V SUPPLY RLOAD (pin 8) to V+(pin 7); a 0.1µF capacitor will reduce charge pump feedthrough to negligible levels. The LTC1152 in- 1152 F02 cludes an internal diode from pin 8 to pin 7 to prevent
Figure 2. LTC1152 Output Resistance Model
external parasitic capacitance from lengthening start-up 6