Datasheet AD8372 (Analog Devices) - 5

Data Sheet AD8372 SERIAL CONTROL INTERFACE TIMING tCLK tPW CLK1 OR CLK2 tLH tLS LCH1 OR LCH2 tDS tDH SDI1 OR SDI2 WRITE BIT DON'T CARE LSB LSB + 1 LSB + 2 MSB – 2 MSB – 1 MSB NOTES 1. THE FIRST SDI BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL GAIN WORD REGISTER. FOR A
003
WRITE OPERATION, THE FIRST BIT SHOULD BE A LOGIC 1. THE GAIN WORD BIT IS THEN REGISTERED INTO THE SDI PIN ON CONSECUTIVE RISING EDGES OF THE CLOCK.
07051- Figure 2. Write Mode Timing Diagram
t t tLH PW CLK tD CLK1 OR CLK2 tLS LCH1 OR LCH2 tDS tDH SDI1 OR SDI2 READ BIT DC DC DC DC DC DC DC SDO1 OR SDO2 LSB LSB + 1 LSB + 2 MSB – 2 MSB – 1 MSB
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NOTES 1. THE FIRST SDI BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL GAIN WORD REGISTER. FOR A
07051-
READ OPERATION, THE FIRST BIT SHOULD BE A LOGIC 0. THE GAIN WORD BIT IS THEN UPDATED AT THE SDO PIN ON CONSECUTIVE FALLING EDGES OF THE CLOCK.
Figure 3. Read Mode Timing Diagram
Table 3. Serial Programming Timing Parameters Parameter Min Unit
Clock Pulse Width (tPW) 10 ns Clock Period (tCK) 20 ns Write Mode Setup Time Data vs. Clock (tDS) 0.0 ns Hold Time Data vs. Clock (tDH) 1.6 ns Setup Time Latch vs. Clock (tLS) −1.8 ns Hold Time Latch vs. Clock (tLH) 2.0 ns Read Mode Clock to Data Out (tD) 4.5 ns Rev. C | Page 5 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS SERIAL CONTROL INTERFACE TIMING ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SINGLE-ENDED AND DIFFERENTIAL SIGNALS PASSIVE FILTER TECHNIQUES DIGITAL GAIN CONTROL DRIVING ANALOG-TO-DIGITAL CONVERTERS EVALUATION BOARD SCHEMATIC OUTLINE DIMENSIONS ORDERING GUIDE