Datasheet LTC6410-6 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Low Distortion, Low Noise Differential IF Amplifier with Configurable Input Impedance |
| Pages / Page | 16 / 10 — PIN FUNCTIONS. V– (Pins 1, 4, 9, 12, 17):. SHDN (Pin 11):. –TERM (Pin … |
| File Format / Size | PDF / 359 Kb |
| Document Language | English |
PIN FUNCTIONS. V– (Pins 1, 4, 9, 12, 17):. SHDN (Pin 11):. –TERM (Pin 13):. VBIAS (Pin 2):. –IN (Pin 14):. +IN (Pin 15):
Model Line for this Datasheet
Text Version of Document
LTC6410-6
PIN FUNCTIONS V– (Pins 1, 4, 9, 12, 17):
Negative Power Supply (Normally
SHDN (Pin 11):
This pin is internally pulled high by a typi- Tied to Ground). All 5 pins must be tied to the same voltage. cally 30k resistor to V+. By pulling this pin low the supply V– maybe tied to a voltage other than ground as long as the current will be reduced to typically 3mA. See DC Electrical voltage between V+ and V– is 2.8V to 5.5V. If the V– pins Characteristics table for the specifi c logic levels. are not tied to ground, bypass each with 680pF and 0.1μF
–TERM (Pin 13):
Negative Input Termination. When tied capacitors as close to the package as possible. directly to –IN, it provides an active 50Ω differential ter-
VBIAS (Pin 2):
This pin sets the input and output com- mination when +TERM is also tied directly to +IN. mon mode voltage by driving the +IN and –IN through a
–IN (Pin 14):
Negative Input. This pin is normally tied to buffer with a high output resistance of 1k. If the part is –TERM, the input termination pin. If AC-coupled, this pin AC-coupled at the input, the VBIAS will set the VINCM and will self bias by V therefore the V BIAS. OUTCM voltage. If the part is DC-coupled at the input, V
+IN (Pin 15):
Positive Input. This pin is normally tied to BIAS should be left fl oating. Internal resistors bias V +TERM, the input termination pin. If AC-coupled, this pin BIAS to 1.4V on a 3V supply. will self bias by V
V+ (Pins 3, 5, 8, 10):
Positive Power Supply. All 4 pins BIAS. must be tied to the same voltage. Split supplies are pos-
+TERM (Pin 16):
Positive Input Termination. When tied sible as long as the voltage between V+ and V– is 2.8V to directly to +IN, it provides an active 50Ω differential ter- 5.5V. Bypass capacitors of 680pF and 0.1μF as close to the mination when –TERM is also tied directly to –IN. part as possible should be used between supplies.
Exposed Pad (Pin 17):
V–. The Exposed Pad must be
+OUT, –OUT (Pins 6, 7):
Outputs. These pins each have soldered to the PCB metal. internal series termination resistors forming a differential output resistance.
BLOCK DIAGRAM
CEXT R (OPT) EXT RT (OPT) 110Ω –TERM –IN –IN V+ RO 1k 11Ω –OUT 6.4k – – VBIAS R +1 O AV = 2.7V/V 11Ω +OUT 0.1μF 5.7k + + 1k +IN V– +IN RT 110Ω +TERM REXT CEXT (OPT) 64106 BD (OPT) 64106fa 10
PIN FUNCTIONS V– (Pins 1, 4, 9, 12, 17):
Negative Power Supply (Normally
SHDN (Pin 11):
This pin is internally pulled high by a typi- Tied to Ground). All 5 pins must be tied to the same voltage. cally 30k resistor to V+. By pulling this pin low the supply V– maybe tied to a voltage other than ground as long as the current will be reduced to typically 3mA. See DC Electrical voltage between V+ and V– is 2.8V to 5.5V. If the V– pins Characteristics table for the specifi c logic levels. are not tied to ground, bypass each with 680pF and 0.1μF
–TERM (Pin 13):
Negative Input Termination. When tied capacitors as close to the package as possible. directly to –IN, it provides an active 50Ω differential ter-
VBIAS (Pin 2):
This pin sets the input and output com- mination when +TERM is also tied directly to +IN. mon mode voltage by driving the +IN and –IN through a
–IN (Pin 14):
Negative Input. This pin is normally tied to buffer with a high output resistance of 1k. If the part is –TERM, the input termination pin. If AC-coupled, this pin AC-coupled at the input, the VBIAS will set the VINCM and will self bias by V therefore the V BIAS. OUTCM voltage. If the part is DC-coupled at the input, V
+IN (Pin 15):
Positive Input. This pin is normally tied to BIAS should be left fl oating. Internal resistors bias V +TERM, the input termination pin. If AC-coupled, this pin BIAS to 1.4V on a 3V supply. will self bias by V
V+ (Pins 3, 5, 8, 10):
Positive Power Supply. All 4 pins BIAS. must be tied to the same voltage. Split supplies are pos-
+TERM (Pin 16):
Positive Input Termination. When tied sible as long as the voltage between V+ and V– is 2.8V to directly to +IN, it provides an active 50Ω differential ter- 5.5V. Bypass capacitors of 680pF and 0.1μF as close to the mination when –TERM is also tied directly to –IN. part as possible should be used between supplies.
Exposed Pad (Pin 17):
V–. The Exposed Pad must be
+OUT, –OUT (Pins 6, 7):
Outputs. These pins each have soldered to the PCB metal. internal series termination resistors forming a differential output resistance.
BLOCK DIAGRAM
CEXT R (OPT) EXT RT (OPT) 110Ω –TERM –IN –IN V+ RO 1k 11Ω –OUT 6.4k – – VBIAS R +1 O AV = 2.7V/V 11Ω +OUT 0.1μF 5.7k + + 1k +IN V– +IN RT 110Ω +TERM REXT CEXT (OPT) 64106 BD (OPT) 64106fa 10
