Datasheet LT1469-2 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Dual 200MHz, 30V/μs 16-Bit Accurate AV ≥ 2 Op Amp |
| Pages / Page | 12 / 10 — APPLICATIONS INFORMATION. Input Considerations. Total Input Noise. … |
| File Format / Size | PDF / 201 Kb |
| Document Language | English |
APPLICATIONS INFORMATION. Input Considerations. Total Input Noise. SIMPLIFIED SCHEMATIC
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LT1469-2
APPLICATIONS INFORMATION Input Considerations
The input bias currents vary with common mode voltage. The cancellation circuitry was not designed to track this Each input of the LT1469 is protected with a 100Ω series common mode voltage because the settling time would resistor and back-to-back diodes across the bases of have been adversely affected. the input devices. If large differential input voltages are anticipated, limit the input current to less than 10mA with The LT1469 inputs can be driven to the negative supply an external series resistor. Each input also has two ESD and to within 0.5V of the positive supply without phase clamp diodes—one to each supply. If an input is driven reversal. As the input moves closer than 0.5V to the posi- beyond the supply, limit the current with an external resis- tive supply, the output reverses phase. tor to less than 10mA.
Total Input Noise
The LT1469 employs bias current cancellation at the inputs. The inverting input current is trimmed at zero common The total input noise of the LT1469 is optimized for a source mode voltage to minimize errors in inverting applications resistance between 1k and 20k. Within this range, the such as I-to-V converters. The noninverting input current total input noise is dominated by the noise of the source is not trimmed and has a wider variation and therefore a resistance itself. When the source resistance is below larger maximum value. As the input offset current can be 1k, voltage noise of the amplifi er dominates. When the greater than either input current, the use of balanced source source resistance is above 20k, the input noise current is resistance is NOT recommended as it actually degrades the dominant contributor. DC accuracy and also increases noise.
SIMPLIFIED SCHEMATIC
V+ I1 I2 I5 Q10 Q8 Q9 OUT +IN Q1 Q2 –IN Q5 Q6 Q7 Q11 Q4 Q3 BIAS C I3 I4 I6 V– 14692 SS 14692f 10
APPLICATIONS INFORMATION Input Considerations
The input bias currents vary with common mode voltage. The cancellation circuitry was not designed to track this Each input of the LT1469 is protected with a 100Ω series common mode voltage because the settling time would resistor and back-to-back diodes across the bases of have been adversely affected. the input devices. If large differential input voltages are anticipated, limit the input current to less than 10mA with The LT1469 inputs can be driven to the negative supply an external series resistor. Each input also has two ESD and to within 0.5V of the positive supply without phase clamp diodes—one to each supply. If an input is driven reversal. As the input moves closer than 0.5V to the posi- beyond the supply, limit the current with an external resis- tive supply, the output reverses phase. tor to less than 10mA.
Total Input Noise
The LT1469 employs bias current cancellation at the inputs. The inverting input current is trimmed at zero common The total input noise of the LT1469 is optimized for a source mode voltage to minimize errors in inverting applications resistance between 1k and 20k. Within this range, the such as I-to-V converters. The noninverting input current total input noise is dominated by the noise of the source is not trimmed and has a wider variation and therefore a resistance itself. When the source resistance is below larger maximum value. As the input offset current can be 1k, voltage noise of the amplifi er dominates. When the greater than either input current, the use of balanced source source resistance is above 20k, the input noise current is resistance is NOT recommended as it actually degrades the dominant contributor. DC accuracy and also increases noise.
SIMPLIFIED SCHEMATIC
V+ I1 I2 I5 Q10 Q8 Q9 OUT +IN Q1 Q2 –IN Q5 Q6 Q7 Q11 Q4 Q3 BIAS C I3 I4 I6 V– 14692 SS 14692f 10
