Datasheet LT1364, LT1365 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Dual and Quad 70MHz, 1000V/µs Op Amps |
| Pages / Page | 12 / 10 — APPLICATIONS INFORMATION. a comparator, peak detector or other open-loop … |
| File Format / Size | PDF / 230 Kb |
| Document Language | English |
APPLICATIONS INFORMATION. a comparator, peak detector or other open-loop applica-
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LT1364/LT1365
U U W U APPLICATIONS INFORMATION a comparator, peak detector or other open-loop applica-
output step in a gain of 10 has only a 1V input step,
tion with large, sustained differential inputs
. Under whereas the same output step in unity gain has a 10 times normal, closed-loop operation, an increase of power dis- greater input step. The curve of Slew Rate vs Input Level sipation is only noticeable in applications with large slewing illustrates this relationship. The LT1364/LT1365 are tested outputs and is proportional to the magnitude of the for slew rate in a gain of –2 so higher slew rates can be differential input voltage and the percent of the time that expected in gains of 1 and –1, and lower slew rates in the inputs are apart. Measure the average supply current higher gain configurations. for the application in order to calculate the power dissipa- The RC network across the output stage is bootstrapped tion. when the amplifier is driving a light or moderate load and has no effect under normal operation. When driving a
Capacitive Loading
capacitive load (or a low value resistive load) the network The LT1364/LT1365 are stable with any capacitive load. is incompletely bootstrapped and adds to the compensa- This is accomplished by sensing the load induced output tion at the high impedance node. The added capacitance pole and adding compensation at the amplifier gain node. slows down the amplifier which improves the phase As the capacitive load increases, both the bandwidth and margin by moving the unity-gain frequency away from the phase margin decrease so there will be peaking in the pole formed by the output impedance and the capacitive frequency domain and in the transient response as shown load. The zero created by the RC combination adds phase in the typical performance curves. The photo of the small to ensure that even for very large load capacitances, the signal response with 200pF load shows 62% peaking. The total phase lag can never exceed 180 degrees (zero phase large signal response shows the output slew rate being margin) and the amplifier remains stable. limited to 10V/µs by the short-circuit current. Coaxial cable can be driven directly, but for best pulse fidelity a
Power Dissipation
resistor of value equal to the characteristic impedance of The LT1364/LT1365 combine high speed and large output the cable (i.e., 75Ω) should be placed in series with the drive in small packages. Because of the wide supply output. The other end of the cable should be terminated voltage range, it is possible to exceed the maximum with the same value resistor to ground. junction temperature under certain conditions. Maximum junction temperature (T
Circuit Operation
J) is calculated from the ambient temperature (TA) and power dissipation (PD) as follows: The LT1364/LT1365 circuit topology is a true voltage feedback amplifier that has the slewing behavior of a LT1364CN8: TJ = TA + (PD x 130°C/W) current feedback amplifier. The operation of the circuit can LT1364CS8: TJ = TA + (PD x 190°C/W) be understood by referring to the simplified schematic. LT1365CN: TJ = TA + (PD x 110°C/W) The inputs are buffered by complementary NPN and PNP LT1365CS: TJ = TA + (PD x 150°C/W) emitter followers which drive a 500Ω resistor. The input voltage appears across the resistor generating currents Worst case power dissipation occurs at the maximum which are mirrored into the high impedance node. Comple- supply current and when the output voltage is at 1/2 of mentary followers form an output stage which buffers the either supply voltage (or the maximum swing if less than gain node from the load. The bandwidth is set by the input 1/2 supply voltage). For each amplifier PDMAX is: resistor and the capacitance on the high impedance node. P The slew rate is determined by the current available to DMAX = (V+ – V–)(ISMAX) + (V+/2)2/RL charge the gain node capacitance. This current is the Example: LT1365 in S16 at 70°C, VS = ±5V, RL = 150W differential input voltage divided by R1, so the slew rate is P proportional to the input. Highest slew rates are therefore DMAX = (10V)(8.4mA) + (2.5V)2/150Ω = 126mW seen in the lowest gain configurations. For example, a 10V TJMAX = 70°C + (4 x 126mW)(150°C/W) = 145°C 10
U U W U APPLICATIONS INFORMATION a comparator, peak detector or other open-loop applica-
output step in a gain of 10 has only a 1V input step,
tion with large, sustained differential inputs
. Under whereas the same output step in unity gain has a 10 times normal, closed-loop operation, an increase of power dis- greater input step. The curve of Slew Rate vs Input Level sipation is only noticeable in applications with large slewing illustrates this relationship. The LT1364/LT1365 are tested outputs and is proportional to the magnitude of the for slew rate in a gain of –2 so higher slew rates can be differential input voltage and the percent of the time that expected in gains of 1 and –1, and lower slew rates in the inputs are apart. Measure the average supply current higher gain configurations. for the application in order to calculate the power dissipa- The RC network across the output stage is bootstrapped tion. when the amplifier is driving a light or moderate load and has no effect under normal operation. When driving a
Capacitive Loading
capacitive load (or a low value resistive load) the network The LT1364/LT1365 are stable with any capacitive load. is incompletely bootstrapped and adds to the compensa- This is accomplished by sensing the load induced output tion at the high impedance node. The added capacitance pole and adding compensation at the amplifier gain node. slows down the amplifier which improves the phase As the capacitive load increases, both the bandwidth and margin by moving the unity-gain frequency away from the phase margin decrease so there will be peaking in the pole formed by the output impedance and the capacitive frequency domain and in the transient response as shown load. The zero created by the RC combination adds phase in the typical performance curves. The photo of the small to ensure that even for very large load capacitances, the signal response with 200pF load shows 62% peaking. The total phase lag can never exceed 180 degrees (zero phase large signal response shows the output slew rate being margin) and the amplifier remains stable. limited to 10V/µs by the short-circuit current. Coaxial cable can be driven directly, but for best pulse fidelity a
Power Dissipation
resistor of value equal to the characteristic impedance of The LT1364/LT1365 combine high speed and large output the cable (i.e., 75Ω) should be placed in series with the drive in small packages. Because of the wide supply output. The other end of the cable should be terminated voltage range, it is possible to exceed the maximum with the same value resistor to ground. junction temperature under certain conditions. Maximum junction temperature (T
Circuit Operation
J) is calculated from the ambient temperature (TA) and power dissipation (PD) as follows: The LT1364/LT1365 circuit topology is a true voltage feedback amplifier that has the slewing behavior of a LT1364CN8: TJ = TA + (PD x 130°C/W) current feedback amplifier. The operation of the circuit can LT1364CS8: TJ = TA + (PD x 190°C/W) be understood by referring to the simplified schematic. LT1365CN: TJ = TA + (PD x 110°C/W) The inputs are buffered by complementary NPN and PNP LT1365CS: TJ = TA + (PD x 150°C/W) emitter followers which drive a 500Ω resistor. The input voltage appears across the resistor generating currents Worst case power dissipation occurs at the maximum which are mirrored into the high impedance node. Comple- supply current and when the output voltage is at 1/2 of mentary followers form an output stage which buffers the either supply voltage (or the maximum swing if less than gain node from the load. The bandwidth is set by the input 1/2 supply voltage). For each amplifier PDMAX is: resistor and the capacitance on the high impedance node. P The slew rate is determined by the current available to DMAX = (V+ – V–)(ISMAX) + (V+/2)2/RL charge the gain node capacitance. This current is the Example: LT1365 in S16 at 70°C, VS = ±5V, RL = 150W differential input voltage divided by R1, so the slew rate is P proportional to the input. Highest slew rates are therefore DMAX = (10V)(8.4mA) + (2.5V)2/150Ω = 126mW seen in the lowest gain configurations. For example, a 10V TJMAX = 70°C + (4 x 126mW)(150°C/W) = 145°C 10
