Datasheet LT1191 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Ultrahigh Speed Operational Amplifier |
| Pages / Page | 12 / 8 — APPLICATIO S I FOR ATIO. Power Supply Bypassing. No Supply Bypass … |
| File Format / Size | PDF / 262 Kb |
| Document Language | English |
APPLICATIO S I FOR ATIO. Power Supply Bypassing. No Supply Bypass Capacitors. Settling Time Poor Bypass
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LT1191
U U W U APPLICATIO S I FOR ATIO Power Supply Bypassing
In most applications, and those requiring good settling The LT1191 is quite tolerant of power supply bypassing. In time, it is important to use multiple bypass capacitors. A some applications a 0.1µF ceramic disc capacitor placed 0.1µF ceramic disc in parallel with a 4.7µF tantalum is 1/2 inch from the amplifier is all that is required. A scope recommended. Two oscilloscope photos with different photo of the amplifier output with no supply bypassing is bypass conditions are used to illustrate the settling time used to demonstrate this bypassing tolerance, R characteristics of the amplifier. Note that although the L = 1kΩ. output waveform looks acceptable at 1V/DIV, when ampli- fied to1mV/DIV the settling time to 2mV is 2.61µs for the
No Supply Bypass Capacitors
0.1µF bypass; the time drops to 143ns with multiple bypass capacitors.
Settling Time Poor Bypass
VOUT VOUT 0V 0V 1V/DIV 1mV/DIV LT1191 • TA04 AV = –1, IN DEMO BOARD, RL = 1kΩ Supply bypassing can also affect the response in the frequency domain. It is possible to see a slight rise in the frequency response at 130MHz depending on the gain LT1191 • TA06 configuration, supply bypass, inductance in the supply SETTLING TIME TO 2mV, AV = –1 SUPPLY BYPASS CAPACITORS = 0.1µF leads and printed circuit board layout. This can be further minimized by not using a socket.
Settling Time Good Bypass Closed-Loop Voltage Gain vs Frequency
20 VS = ±5V TA = 25°C RL = 1k 10 A = 2 V V V A = 1 OUT OUT V 0V 1V/DIV 0V 1mV/DIV 0 –10 CLOSED-LOOP VOLTAGE GAIN (dB) –20 LT1191 • TA07 100k 1M 10M 100M 1G SETTLING TIME TO 2mV, A FREQUENCY (Hz) V = –1 SUPPLY BYPASS CAPACITORS = 0.1µF + 4.7µF TANTALUM LT1191 • TA05 8
U U W U APPLICATIO S I FOR ATIO Power Supply Bypassing
In most applications, and those requiring good settling The LT1191 is quite tolerant of power supply bypassing. In time, it is important to use multiple bypass capacitors. A some applications a 0.1µF ceramic disc capacitor placed 0.1µF ceramic disc in parallel with a 4.7µF tantalum is 1/2 inch from the amplifier is all that is required. A scope recommended. Two oscilloscope photos with different photo of the amplifier output with no supply bypassing is bypass conditions are used to illustrate the settling time used to demonstrate this bypassing tolerance, R characteristics of the amplifier. Note that although the L = 1kΩ. output waveform looks acceptable at 1V/DIV, when ampli- fied to1mV/DIV the settling time to 2mV is 2.61µs for the
No Supply Bypass Capacitors
0.1µF bypass; the time drops to 143ns with multiple bypass capacitors.
Settling Time Poor Bypass
VOUT VOUT 0V 0V 1V/DIV 1mV/DIV LT1191 • TA04 AV = –1, IN DEMO BOARD, RL = 1kΩ Supply bypassing can also affect the response in the frequency domain. It is possible to see a slight rise in the frequency response at 130MHz depending on the gain LT1191 • TA06 configuration, supply bypass, inductance in the supply SETTLING TIME TO 2mV, AV = –1 SUPPLY BYPASS CAPACITORS = 0.1µF leads and printed circuit board layout. This can be further minimized by not using a socket.
Settling Time Good Bypass Closed-Loop Voltage Gain vs Frequency
20 VS = ±5V TA = 25°C RL = 1k 10 A = 2 V V V A = 1 OUT OUT V 0V 1V/DIV 0V 1mV/DIV 0 –10 CLOSED-LOOP VOLTAGE GAIN (dB) –20 LT1191 • TA07 100k 1M 10M 100M 1G SETTLING TIME TO 2mV, A FREQUENCY (Hz) V = –1 SUPPLY BYPASS CAPACITORS = 0.1µF + 4.7µF TANTALUM LT1191 • TA05 8
