Datasheet ADP5053 (Analog Devices) - 9

Data Sheet ADP5053 ABSOLUTE MAXIMUM RATINGS Table 5.
Stresses at or above those listed under Absolute Maximum
Parameter Rating
Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these PVIN1 to PGND −0.3 V to +18 V or any other conditions above those indicated in the operational PVIN2 to PGND −0.3 V to +18 V section of this specification is not implied. Operation beyond PVIN3 to PGND3 −0.3 V to +18 V the maximum operating conditions for extended periods may PVIN4 to PGND4 −0.3 V to +18 V affect product reliability. SW1 to PGND −0.3 V to +18 V SW2 to PGND −0.3 V to +18 V
THERMAL RESISTANCE
SW3 to PGND3 −0.3 V to +18 V θJA is specified for the worst-case conditions, that is, a device SW4 to PGND4 −0.3 V to +18 V soldered in a circuit board for surface-mount packages. PGND to GND −0.3 V to +0.3 V PGND3 to GND −0.3 V to +0.3 V
Table 6. Thermal Resistance
PGND4 to GND −0.3 V to +0.3 V
Package Type θJA θJC Unit
BST1 to SW1 −0.3 V to +6.5 V 48-Lead LFCSP 27.87 2.99 °C/W BST2 to SW2 −0.3 V to +6.5 V BST3 to SW3 −0.3 V to +6.5 V BST4 to SW4 −0.3 V to +6.5 V
ESD CAUTION
DL1 to PGND −0.3 V to +6.5 V DL2 to PGND −0.3 V to +6.5 V SS12, SS34 to GND −0.3 V to +6.5 V EN1, EN2, EN3, EN4 to GND −0.3 V to +6.5 V VREG to GND −0.3 V to +6.5 V SYNC/MODE to GND −0.3 V to +6.5 V WDI, RSTO, VTH to GND −0.3 V to +6.5 V MR to GND −0.3 V to +3.6 V RT to GND −0.3 V to +3.6 V PWRGD to GND −0.3 V to +6.5 V FB1, FB2, FB3, FB4 to GND1 −0.3 V to +3.6 V FB2 to GND2 −0.3 V to +6.5 V FB4 to GND2 −0.3 V to +7 V COMP1, COMP2, COMP3, COMP4 to GND −0.3 V to +3.6 V VDD to GND −0.3 V to +3.6 V Storage Temperate Range −65°C to +150°C Operational Junction Temperature Range −40°C to +125°C 1 This rating applies to the adjustable output voltage models of the ADP5053. 2 This rating applies to the fixed output voltage models of the ADP5053. Rev. C | Page 9 of 37 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS SUPERVISORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES Pulse-Width Modulation (PWM) Mode Power Save Mode (PSM) Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGES INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK Pulse Skip Mode Under Maximum Duty Cycle HICCUP PROTECTION LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode Overvoltage Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION THERMAL SHUTDOWN SUPERVISORY CIRCUIT Reset Output Watchdog Input Manual Reset Input Processor Manual Reset Mode Power On/Off Switch Mode APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL PROGRAMMING THE ADJUSTABLE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown JUNCTION TEMPERATURE DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR RECOMMENDED EXTERNAL COMPONENTS CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE