Datasheet ADP5051 (Analog Devices)

Integrated Power Solution with Quad Buck Regulators, Supervisory Circuit, and I2C Interface Data Sheet ADP5051 FEATURES TYPICAL APPLICATION CIRCUIT Wide input voltage range: 4.5 V to 15.0 V ADP5051 VREG SYNC/MODE ±1.5% output accuracy over full temperature range INT VREG VDD OSCILLATOR C1 100mA RT C0 250 kHz to 1.4 MHz adjustable switching frequency FB1 PVIN1 Adjustable/fixed output options via factory fuse or I2C interface 4.5V TO 15V BST1 SW1 CHANNEL 1 C3 I L1 2C interface with interrupt on fault conditions C2 VOUT1 BUCK COMP1 (4A) VREG Power regulation C4 EN1 Q1 DL1 Channel 1 and Channel 2: programmable 1.2 A/2.5 A/4 A SS12 RILIM1 PGND sync buck regulators with low-side FET driver RILIM2 DL2 Channel 3 and Channel 4: 1.2 A sync buck regulators Q2 PVIN2 C5 CHANNEL 2 VREG VOUT2 SW2 Single 8 A output (Channel 1 and Channel 2 in parallel) BUCK COMP2 (4A) L2 C6 C7 Dynamic voltage scaling (DVS) for Channel 1 and Channel 4 BST2 EN2 FB2 Precision enable with 0.8 V accurate threshold Active output discharge switch PVIN3 BST3 C8 C9 L3 VOUT3 Programmable phase shift in 90° steps COMP3 CHANNEL 3 SW3 BUCK (1.2A) C10 FB3 Individual channel FPWM/PSM selection EN3 PGND3 Frequency synchronization input or output SS34 BST4 Optional latch-off protection on OVP/OCP failure PVIN4 C12 L4 VOUT4 Power-good flag on selected channels SW4 CHANNEL 4 C11 BUCK COMP4 (1.2A) C13 FB4 Low input voltage detection EN4 PGND4 VREG Open-drain processor reset with external adjustable threshold WDI RSTO monitoring WATCHDOG MR AND VTH RESET VOUTx Watchdog refresh input VDDIO PWRGD Manual reset input I2C ALERT SCL INT SDA Overheat detection on junction temperature
001
EXPOSED PAD
1635-
UVLO, OCP, and TSD protection
1 Figure 1.
APPLICATIONS
Combining Channel 1 and Channel 2 in a paral el configuration
Small cell base stations
provides a single output with up to 8 A of current. Channel 3 and
FPGA and processor applications
Channel 4 integrate both high-side and low-side MOSFETs to
Security and surveillance
deliver an output current of 1.2 A.
Medical applications
The ADP5051 supervisory circuits monitor the voltage level.
GENERAL DESCRIPTION
The watchdog timer generates a reset when the WDI pin does not toggle within a preset timeout period. Select manual reset The ADP5051 combines four high performance buck regulators functionality via the processor reset mode or system power on/off and a supervisory circuit with a voltage monitor, a watchdog switch mode. function, and a manual reset in a 48-lead LFCSP package that meets demanding performance and board space requirements. The optional I2C interface offers flexible configurations, including The device enables direct connection to high input voltages up to adjustable and fixed output voltage, junction temperature overheat 15.0 V with no preregulators. warning, low input voltage detection, and dynamic voltage scaling. Channel 1 and Channel 2 integrate high-side power MOSFET and
Table 1. Family Models
low-side MOSFET drivers. In low-side power devices, use external
Model Channels I2C Package
NFETs to achieve an efficiency optimized solution and deliver a ADP5050 Four bucks, one LDO Yes 48-Lead LFCSP programmable output current of 1.2 A, 2.5 A, or 4 A. ADP5051 Four bucks, supervisory Yes 48-Lead LFCSP ADP5052 Four bucks, one LDO No 48-Lead LFCSP ADP5053 Four bucks, supervisory No 48-Lead LFCSP ADP5054 Four high current bucks No 48-Lead LFCSP
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS SUPERVISORY SPECIFICATIONS I2C INTERFACE TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES Pulse-Width Modulation (PWM) Mode Power Save Mode (PSM) Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGES DYNAMIC VOLTAGE SCALING (DVS) INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK Pulse Skip Mode Under Maximum Duty Cycle HICCUP PROTECTION LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode Overvoltage Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION INTERRUPT FUNCTION THERMAL SHUTDOWN OVERHEAT DETECTION LOW INPUT VOLTAGE DETECTION SUPERVISORY CIRCUIT Reset Output Watchdog Input Manual Reset Input Processor Manual Reset Mode Power On/Off Switch Mode I2C INTERFACE SDA AND SCL PINS I2C ADDRESSES SELF-CLEAR REGISTER BITS I2C INTERFACE TIMING DIAGRAMS APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL PROGRAMMING THE ADJUSTABLE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown JUNCTION TEMPERATURE DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR RECOMMENDED EXTERNAL COMPONENTS CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS REGISTER MAP DETAILED REGISTER DESCRIPTIONS REGISTER 1: PCTRL (CHANNEL ENABLE CONTROL), ADDRESS 0x01 REGISTER 2: VID1 (VID SETTING FOR CHANNEL 1), ADDRESS 0x02 REGISTER 3: VID23 (VID SETTING FOR CHANNEL 2 AND CHANNEL 3), ADDRESS 0x03 REGISTER 4: VID4 (VID SETTING FOR CHANNEL 4), ADDRESS 0x04 REGISTER 5: DVS_CFG (DVS CONFIGURATION FOR CHANNEL 1 AND CHANNEL 4), ADDRESS 0x05 REGISTER 6: OPT_CFG (FPWM/PSM MODE AND OUTPUT DISCHARGE FUNCTION CONFIGURATION), ADDRESS 0x06 REGISTER 7: LCH_CFG (SHORT-CIRCUIT LATCH-OFF AND OVERVOLTAGE LATCH-OFF CONFIGURATION), ADDRESS 0x07 REGISTER 8: SW_CFG (SWITCHING FREQUENCY AND PHASE SHIFT CONFIGURATION), ADDRESS 0x08 REGISTER 9: TH_CFG (TEMPERATURE WARNING AND LOW VIN WARNING THRESHOLD CONFIGURATION), ADDRESS 0x09 REGISTER 10: HICCUP_CFG (HICCUP CONFIGURATION), ADDRESS 0x0A REGISTER 11: PWRGD_MASK (CHANNEL MASK CONFIGURATION FOR PWRGD PIN), ADDRESS 0x0B REGISTER 12: LCH_STATUS (LATCH-OFF STATUS READBACK), ADDRESS 0x0C REGISTER 13: STATUS_RD (STATUS READBACK), ADDRESS 0x0D REGISTER 14: INT_STATUS (INTERRUPT STATUS READBACK), ADDRESS 0x0E REGISTER 15: INT_MASK (INTERRUPT MASK CONFIGURATION), ADDRESS 0x0F REGISTER 16: FORCE_SHUT (FORCED SHUT DOWN), ADDRESS 0x10 REGISTER 17: DEFAULT_SET (DEFAULT RESET), ADDRESS 0x11 FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE