Datasheet ADP5040 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | Micro PMU with 1.2 A Buck Regulator and Two 300 mA LDOs |
| Pages / Page | 37 / 1 — Micro PMU with 1.2 A Buck Regulator. and Two 300 mA LDOs. Data Sheet. … |
| Revision | D |
| File Format / Size | PDF / 3.8 Mb |
| Document Language | English |
Micro PMU with 1.2 A Buck Regulator. and Two 300 mA LDOs. Data Sheet. ADP5040. FEATURES. GENERAL DESCRIPTION
Text Version of Document
Micro PMU with 1.2 A Buck Regulator and Two 300 mA LDOs Data Sheet ADP5040 FEATURES GENERAL DESCRIPTION Input voltage range: 2.3 V to 5.5 V
The ADP5040 combines one high performance buck regulator
One 1.2 A buck regulator
and two low dropout regulators (LDO) in a small 20-lead
Two 300 mA LDOs
LFCSP to meet demanding performance and board space
20-lead, 4 mm × 4 mm LFCSP package
requirements.
Overcurrent and thermal protection
The high switching frequency of the buck regulator enables the use
Soft start
of tiny multilayer external components and minimizes board space.
Undervoltage lockout Buck key specifications
When the MODE pin is set to logic high, the buck regulator
Output voltage range: 0.8 V to 3.8 V
operates in forced pulse width modulation (PWM) mode. When
Current mode topology for excellent transient response
the MODE pin is set to logic low, the buck regulator operates in
3 MHz operating frequency
PWM mode when the load is around the nominal value. When
Peak efficiency up to 96%
the load current falls below a predefined threshold the regulator
Uses tiny multilayer inductors and capacitors
operates in power save mode (PSM) improving the light-load
Mode pin selects forced PWM or auto PWM/PSM modes
efficiency. The low quiescent current, low dropout voltage, and
100% duty cycle low dropout mode
wide input voltage range of the ADP5040 LDOs extend the
LDOs key specifications
battery life of portable devices. The ADP5040 LDOs maintain
Output voltage range: 0.8 V to 5.2 V
a power supply rejection greater than 60 dB for frequencies as
Low V
high as 10 kHz while operating with a low headroom voltage.
IN from 1.7 V to 5.5 V Stable with 2.2 μF ceramic output capacitors
Each regulator in the ADP5040 is activated by a high level on
High PSRR
the respective enable pin. The output voltages of the regulators
Low output noise
are programmed though external resistor dividers to address a
Low dropout voltage
variety of applications.
−40°C to +125°C junction temperature range FUNCTIONAL BLOCK DIAGRAM VOUT1 AVIN L1 1µH SW VOUT1 AT FB1 1.2A BUCK AVIN R1 C6 R2 10µF V VIN1 IN1 = 2.3V TO 5.5V PGND C5 4.7µF ON EN_BK FPWM EN1 MODE OFF PSM/PWM VOUT2 VIN2 LDO1 V V OUT2 AT IN2 = 1.7V (DIGITAL) FB2 300mA TO 5.5V C1 C2 EN_LDO1 1µF R3 R4 2.2µF ON EN2 OFF ON EN3 OFF VIN3 EN_LDO2 VOUT3 VIN3 = 1.7V VOUT3 AT TO 5.5V LDO2 300mA C3 FB3 (ANALOG) 1µF R7 C4 R3 2.2µF
1 -00
AGND
65 096 Figure 1.
Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2011–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS GENERAL SPECIFICATIONS BUCK SPECIFICATIONS LDO1, LDO2 SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER MANAGEMENT UNIT Thermal Protection Undervoltage Lockout Enable/Shutdown Active Pull-Down BUCK SECTION Control Scheme PWM Mode Power Save Mode (PSM) PSM Current Threshold Short-Circuit Protection Soft Start Current Limit 100% Duty Operation LDO SECTION APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Feedback Resistors Inductor Output Capacitor Input Capacitor LDO EXTERNAL COMPONENT SELECTION Feedback Resistors Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties POWER DISSIPATION/THERMAL CONSIDERATIONS Buck Regulator Power Dissipation LDO Regulator Power Dissipation Junction Temperature APPLICATION DIAGRAM PCB LAYOUT GUIDELINES SUGGESTED LAYOUT BILL OF MATERIALS FACTORY PROGRAMMABLE OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
The ADP5040 combines one high performance buck regulator
One 1.2 A buck regulator
and two low dropout regulators (LDO) in a small 20-lead
Two 300 mA LDOs
LFCSP to meet demanding performance and board space
20-lead, 4 mm × 4 mm LFCSP package
requirements.
Overcurrent and thermal protection
The high switching frequency of the buck regulator enables the use
Soft start
of tiny multilayer external components and minimizes board space.
Undervoltage lockout Buck key specifications
When the MODE pin is set to logic high, the buck regulator
Output voltage range: 0.8 V to 3.8 V
operates in forced pulse width modulation (PWM) mode. When
Current mode topology for excellent transient response
the MODE pin is set to logic low, the buck regulator operates in
3 MHz operating frequency
PWM mode when the load is around the nominal value. When
Peak efficiency up to 96%
the load current falls below a predefined threshold the regulator
Uses tiny multilayer inductors and capacitors
operates in power save mode (PSM) improving the light-load
Mode pin selects forced PWM or auto PWM/PSM modes
efficiency. The low quiescent current, low dropout voltage, and
100% duty cycle low dropout mode
wide input voltage range of the ADP5040 LDOs extend the
LDOs key specifications
battery life of portable devices. The ADP5040 LDOs maintain
Output voltage range: 0.8 V to 5.2 V
a power supply rejection greater than 60 dB for frequencies as
Low V
high as 10 kHz while operating with a low headroom voltage.
IN from 1.7 V to 5.5 V Stable with 2.2 μF ceramic output capacitors
Each regulator in the ADP5040 is activated by a high level on
High PSRR
the respective enable pin. The output voltages of the regulators
Low output noise
are programmed though external resistor dividers to address a
Low dropout voltage
variety of applications.
−40°C to +125°C junction temperature range FUNCTIONAL BLOCK DIAGRAM VOUT1 AVIN L1 1µH SW VOUT1 AT FB1 1.2A BUCK AVIN R1 C6 R2 10µF V VIN1 IN1 = 2.3V TO 5.5V PGND C5 4.7µF ON EN_BK FPWM EN1 MODE OFF PSM/PWM VOUT2 VIN2 LDO1 V V OUT2 AT IN2 = 1.7V (DIGITAL) FB2 300mA TO 5.5V C1 C2 EN_LDO1 1µF R3 R4 2.2µF ON EN2 OFF ON EN3 OFF VIN3 EN_LDO2 VOUT3 VIN3 = 1.7V VOUT3 AT TO 5.5V LDO2 300mA C3 FB3 (ANALOG) 1µF R7 C4 R3 2.2µF
1 -00
AGND
65 096 Figure 1.
Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2011–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS GENERAL SPECIFICATIONS BUCK SPECIFICATIONS LDO1, LDO2 SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER MANAGEMENT UNIT Thermal Protection Undervoltage Lockout Enable/Shutdown Active Pull-Down BUCK SECTION Control Scheme PWM Mode Power Save Mode (PSM) PSM Current Threshold Short-Circuit Protection Soft Start Current Limit 100% Duty Operation LDO SECTION APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Feedback Resistors Inductor Output Capacitor Input Capacitor LDO EXTERNAL COMPONENT SELECTION Feedback Resistors Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties POWER DISSIPATION/THERMAL CONSIDERATIONS Buck Regulator Power Dissipation LDO Regulator Power Dissipation Junction Temperature APPLICATION DIAGRAM PCB LAYOUT GUIDELINES SUGGESTED LAYOUT BILL OF MATERIALS FACTORY PROGRAMMABLE OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
