Datasheet ADP5022 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Dual 3 MHz, 600 mA Buck Regulator with 150 mA LDO |
| Pages / Page | 28 / 6 — ADP5022. ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating. THERMAL … |
| Revision | C |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
ADP5022. ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating. THERMAL RESISTANCE. THERMAL DATA. Table 5. Thermal Resistance
Model Line for this Datasheet
Text Version of Document
ADP5022 ABSOLUTE MAXIMUM RATINGS Table 4.
θJA of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is
Parameter Rating
highly dependent on the application and board layout. In VDDA, VIN1, VIN2, VIN3, VOUT1, VOUT2, −0.3 V to +6 V VOUT3, EN1, EN2, EN3, MODE to GND applications where high maximum power dissipation exists, Storage Temperature Range −65°C to +150°C close attention to thermal board design is required. The value Operating Junction Temperature Range −40°C to +125°C of θJA may vary, depending on PCB material, layout, and envi- Soldering Conditions JEDEC J-STD-020 ronmental conditions. The specified values of θJA are based on a 4-layer, 4” × 3” circuit board. Refer to JEDEC JESD 51-9 for Stresses above those listed under Absolute Maximum Ratings detailed information on the board construction. For additional may cause permanent damage to the device. This is a stress information, see the AN-617 Application Note, MicroCSPTM rating only; functional operation of the device at these or any Wafer Level Chip Scale Package. other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute
THERMAL RESISTANCE
maximum rating conditions for extended periods may affect θJA is specified for the worst-case conditions, that is, a device device reliability. soldered on a circuit board.
THERMAL DATA Table 5. Thermal Resistance
Absolute maximum ratings apply individually only, not in
Package Type θJA Unit
combination. 16-Ball, 0.5 mm Pitch WLCSP 65 °C/W The ADP5022 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature (T
ESD CAUTION
A) does not guarantee that the junction temperature (TJ) is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature may exceed the maximum limit as long as the junction temperature is within specification limits. TJ of the device is dependent on TA, the power dissipation (PD) of the device, and the junction-to-ambient thermal resistance (θJA) of the package. Maximum TJ is calculated from TA and PD using the following formula: TJ = TA + (PD × θJA) Rev. C | Page 6 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS BUCK1 AND BUCK2 SPECIFICATIONS LDO SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER MANAGEMENT UNIT Thermal Protection Undervoltage Lockout Enable/Shutdown BUCK SECTION Control Scheme PWM Mode Power Save Mode (PSM) PSM Current Threshold Oscillator/Phasing of Inductor Switching Enable/Shutdown Short-Circuit Protection Soft Start Current Limit 100% Duty Operation LDO SECTION LDO Undervoltage Lockout APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Inductor Output Capacitor Input Capacitor LDO CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties PCB LAYOUT GUIDELINES EVALUATION BOARD SCHEMATICS AND ARTWORK SUGGESTED LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE
θJA of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is
Parameter Rating
highly dependent on the application and board layout. In VDDA, VIN1, VIN2, VIN3, VOUT1, VOUT2, −0.3 V to +6 V VOUT3, EN1, EN2, EN3, MODE to GND applications where high maximum power dissipation exists, Storage Temperature Range −65°C to +150°C close attention to thermal board design is required. The value Operating Junction Temperature Range −40°C to +125°C of θJA may vary, depending on PCB material, layout, and envi- Soldering Conditions JEDEC J-STD-020 ronmental conditions. The specified values of θJA are based on a 4-layer, 4” × 3” circuit board. Refer to JEDEC JESD 51-9 for Stresses above those listed under Absolute Maximum Ratings detailed information on the board construction. For additional may cause permanent damage to the device. This is a stress information, see the AN-617 Application Note, MicroCSPTM rating only; functional operation of the device at these or any Wafer Level Chip Scale Package. other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute
THERMAL RESISTANCE
maximum rating conditions for extended periods may affect θJA is specified for the worst-case conditions, that is, a device device reliability. soldered on a circuit board.
THERMAL DATA Table 5. Thermal Resistance
Absolute maximum ratings apply individually only, not in
Package Type θJA Unit
combination. 16-Ball, 0.5 mm Pitch WLCSP 65 °C/W The ADP5022 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature (T
ESD CAUTION
A) does not guarantee that the junction temperature (TJ) is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature may exceed the maximum limit as long as the junction temperature is within specification limits. TJ of the device is dependent on TA, the power dissipation (PD) of the device, and the junction-to-ambient thermal resistance (θJA) of the package. Maximum TJ is calculated from TA and PD using the following formula: TJ = TA + (PD × θJA) Rev. C | Page 6 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS BUCK1 AND BUCK2 SPECIFICATIONS LDO SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER MANAGEMENT UNIT Thermal Protection Undervoltage Lockout Enable/Shutdown BUCK SECTION Control Scheme PWM Mode Power Save Mode (PSM) PSM Current Threshold Oscillator/Phasing of Inductor Switching Enable/Shutdown Short-Circuit Protection Soft Start Current Limit 100% Duty Operation LDO SECTION LDO Undervoltage Lockout APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Inductor Output Capacitor Input Capacitor LDO CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties PCB LAYOUT GUIDELINES EVALUATION BOARD SCHEMATICS AND ARTWORK SUGGESTED LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE
