Datasheet LTC3670 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Monolithic 400mA Buck Regulator with Dual 150mA LDOs in 3mm × 2mm DFN |
| Pages / Page | 14 / 9 — OPERATION. Switch Slew-Rate Control. LOW DROPOUT LINEAR REGULATORS … |
| Revision | A |
| File Format / Size | PDF / 401 Kb |
| Document Language | English |
OPERATION. Switch Slew-Rate Control. LOW DROPOUT LINEAR REGULATORS (LDOs). LOW VIN SUPPLY UNDERVOLTAGE LOCKOUT
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LTC3670
OPERATION Switch Slew-Rate Control
Each LDO can be enabled or disabled via its own enable The buck regulator contains new patent-pending circuitry pin. When disabled with VIN still applied, an internal to limit the slew rate of the switch node (SW pin). This pull-down resistor is switched in to help bring the output new circuitry is designed to transition the switch node to ground. When an LDO is enabled, a soft-start circuit over a period of a couple nanoseconds, significantly ramps its regulation point from zero to final value over a reducing radiated EMI and conducted supply noise while period of roughly 0.1ms, reducing the required VIN inrush maintaining high efficiency. current.
LOW DROPOUT LINEAR REGULATORS (LDOs) LOW VIN SUPPLY UNDERVOLTAGE LOCKOUT
The LTC3670 contains two independent LDO regulators, An undervoltage lockout (UVLO) circuit shuts down the each supporting a load of up to 150mA. Each LDO takes LTC3670 when VIN drops below about 2.2V. power from the VIN pin and drives its output pin with the goal of bringing its feedback pin voltage to 0.8V. In the
POWER GOOD DETECTION
usual case, a resistor divider is connected between the The LTC3670 has a built-in supply monitor. If the feedback LDO’s output pin, feedback pin and ground, in order to voltage of every enabled regulator is above 92% of its close the control loop and program the output voltage. For regulation value, the PGOOD pin becomes high impedance. stability, each LDO output must be bypassed to ground Otherwise, or if no regulators are enabled, the PGOOD pin with a minimum 1µF ceramic capacitor. is driven to ground by an internal open-drain NMOS. The PGOOD pin may be connected through a pull-up resistor to a supply voltage of up to 5.5V, independent of the VIN pin voltage. Rev A For more information www.analog.com 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Typical Application Related Parts
OPERATION Switch Slew-Rate Control
Each LDO can be enabled or disabled via its own enable The buck regulator contains new patent-pending circuitry pin. When disabled with VIN still applied, an internal to limit the slew rate of the switch node (SW pin). This pull-down resistor is switched in to help bring the output new circuitry is designed to transition the switch node to ground. When an LDO is enabled, a soft-start circuit over a period of a couple nanoseconds, significantly ramps its regulation point from zero to final value over a reducing radiated EMI and conducted supply noise while period of roughly 0.1ms, reducing the required VIN inrush maintaining high efficiency. current.
LOW DROPOUT LINEAR REGULATORS (LDOs) LOW VIN SUPPLY UNDERVOLTAGE LOCKOUT
The LTC3670 contains two independent LDO regulators, An undervoltage lockout (UVLO) circuit shuts down the each supporting a load of up to 150mA. Each LDO takes LTC3670 when VIN drops below about 2.2V. power from the VIN pin and drives its output pin with the goal of bringing its feedback pin voltage to 0.8V. In the
POWER GOOD DETECTION
usual case, a resistor divider is connected between the The LTC3670 has a built-in supply monitor. If the feedback LDO’s output pin, feedback pin and ground, in order to voltage of every enabled regulator is above 92% of its close the control loop and program the output voltage. For regulation value, the PGOOD pin becomes high impedance. stability, each LDO output must be bypassed to ground Otherwise, or if no regulators are enabled, the PGOOD pin with a minimum 1µF ceramic capacitor. is driven to ground by an internal open-drain NMOS. The PGOOD pin may be connected through a pull-up resistor to a supply voltage of up to 5.5V, independent of the VIN pin voltage. Rev A For more information www.analog.com 9 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Typical Application Related Parts
