Datasheet LTC3560 (Analog Devices) - 10

LTC3560
APPLICATIONS INFORMATION
0.6V ≤ VOUT ≤ 5.5V 1. The VIN quiescent current is due to two components: the DC bias current as given in the electrical charac- R2 teristics and the internal main switch and synchronous VFB switch gate charge currents. The gate charge current LTC3560 R1 results from switching the gate capacitance of the GND internal power MOSFET switches. Each time the gate 3560 F02 is switched from high to low to high again, a packet of
Figure 2. Setting the LTC3560 Output Voltage
charge, dQ, moves from VIN to ground. The resulting dQ/dt is the current out of VIN that is typically larger
Effi ciency Considerations
than the DC bias current. In continuous mode, IGATECHG = f(Q The effi ciency of a switching regulator is equal to the output T + QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias power divided by the input power times 100%. It is often and gate charge losses are proportional to V useful to analyze individual losses to determine what is IN and thus their effects will be more pronounced at higher supply limiting the effi ciency and which change would produce voltages. the most improvement. Effi ciency can be expressed as: 2. I2R losses are calculated from the resistances of the Effi ciency = 100% – (L1 + L2 + L3 + ...) internal switches, RSW, and external inductor RL. In where L1, L2, etc. are the individual losses as a percentage continuous mode, the average output current fl owing of input power. through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series Although all dissipative elements in the circuit produce resistance looking into the SW pin is a function of both losses, two main sources usually account for most of top and bottom MOSFET R the losses in LTC3560 circuits: V DS(ON) and the duty cycle IN quiescent current and (DC) as follows: I2R losses. The VIN quiescent current loss dominates the effi ciency loss at very low load currents whereas the RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) I2R loss dominates the effi ciency loss at medium to high The R load currents. In a typical effi ciency plot, the effi ciency DS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Charateristics curve at very low load currents can be misleading since curves. Thus, to obtain I2R losses, simply add R the actual power lost is of no consequence as illustrated SW to R in Figure 3. L and multiply the result by the square of the average output current. 1 Other losses including CIN and COUT ESR dissipative losses VOUT = 2.5V Burst Mode OPERATION and inductor core losses generally account for less than 2% total additional loss. 0.1
Thermal Considerations
0.01 In most applications the LTC3560 does not dissipate POWER LOST (W) much heat due to its high effi ciency. But, in applica- 0.001 tions where the LTC3560 is running at high ambient VIN = 3.6V V temperature with low supply voltage and high duty cycles, IN = 4.2V VIN = 5.5V 0.0001 such as in dropout, the heat dissipated may exceed the 0.1 1 10 100 1000 maximum junction temperature of the part. If the junction LOAD CURRENT (mA) 3560 F03 temperature reaches approximately 150°C, both power
Figure 3. Power Lost vs Load Current
3560fb 10