Datasheet LT1943 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | High Current Quad Output Regulator for TFT LCD Panels |
| Pages / Page | 20 / 8 — PI FU CTIO S. SW3 (Pin 21):. E3 (Pin 24):. BIAS (Pin 22):. T (Pin 25):. … |
| File Format / Size | PDF / 278 Kb |
| Document Language | English |
PI FU CTIO S. SW3 (Pin 21):. E3 (Pin 24):. BIAS (Pin 22):. T (Pin 25):. PGOOD (Pin 23):. ON (Pin 26):. SW2 (Pins 27, 28):
Model Line for this Datasheet
Text Version of Document
LT1943
U U U PI FU CTIO S SW3 (Pin 21):
This is the collector of the internal NPN resistor between the source and gate of the P-channel bipolar power transistor for switching regulator 3. Mini- MOSFET keeps it off when switcher 2’s output is low. mize metal trace area at this pin to keep EMI down.
E3 (Pin 24):
This is switching regulator 3’s output and the
BIAS (Pin 22):
The BIAS pin is used to improve efficiency emitter of the output disconnect PNP. Tie the output when operating at higher input voltages. Connecting this capacitor and resistor divider here. pin to the output of switching regulator 1 forces most of
C
the internal circuitry to draw its operating current from
T (Pin 25):
Timing Capacitor Pin. This is the input to the V V ON timer and programs the time delay from all four LOGIC rather than VIN. The drivers of switches 2, 3 and 4 feedback pins reaching 1.125V to V are supplied by BIAS. Switches 2, 3 and 4 will not switch ON turning on. The CT capacitor value can be set using the equation C = (20µA • until the BIAS pin reaches approximately 2.8V. BIAS must t be tied to V DELAY)/1.1V. LOGIC.
V PGOOD (Pin 23):
Power Good Comparator Output. This is
ON (Pin 26):
This is the delayed output for switching regulator 3. V the open collector output of the power good comparator ON reaches its programmed voltage after the internal C and can be used in conjunction with an external P-Channel T timer times out. Protection circuitry ensures VON is disabled if any of the four outputs are more than MOSFET to provide output disconnect for AVDD as shown 10% below normal voltage. in the 5V Input, Quad Output TFT-LCD Power Supply on the last page of the data sheet. When switcher 2’s output
SW2 (Pins 27, 28):
The SW2 pins are the collector of the reaches approximately 90% of its programmed voltage, internal NPN bipolar power transistor for switching regu- PGOOD will be pulled to ground. This will pull down on the lator 2. These pins must be tied together. Minimize trace gate of the MOSFET, connecting AV area at these pins to keep EMI down. DD. A 100k pull-up 1943fa 8
U U U PI FU CTIO S SW3 (Pin 21):
This is the collector of the internal NPN resistor between the source and gate of the P-channel bipolar power transistor for switching regulator 3. Mini- MOSFET keeps it off when switcher 2’s output is low. mize metal trace area at this pin to keep EMI down.
E3 (Pin 24):
This is switching regulator 3’s output and the
BIAS (Pin 22):
The BIAS pin is used to improve efficiency emitter of the output disconnect PNP. Tie the output when operating at higher input voltages. Connecting this capacitor and resistor divider here. pin to the output of switching regulator 1 forces most of
C
the internal circuitry to draw its operating current from
T (Pin 25):
Timing Capacitor Pin. This is the input to the V V ON timer and programs the time delay from all four LOGIC rather than VIN. The drivers of switches 2, 3 and 4 feedback pins reaching 1.125V to V are supplied by BIAS. Switches 2, 3 and 4 will not switch ON turning on. The CT capacitor value can be set using the equation C = (20µA • until the BIAS pin reaches approximately 2.8V. BIAS must t be tied to V DELAY)/1.1V. LOGIC.
V PGOOD (Pin 23):
Power Good Comparator Output. This is
ON (Pin 26):
This is the delayed output for switching regulator 3. V the open collector output of the power good comparator ON reaches its programmed voltage after the internal C and can be used in conjunction with an external P-Channel T timer times out. Protection circuitry ensures VON is disabled if any of the four outputs are more than MOSFET to provide output disconnect for AVDD as shown 10% below normal voltage. in the 5V Input, Quad Output TFT-LCD Power Supply on the last page of the data sheet. When switcher 2’s output
SW2 (Pins 27, 28):
The SW2 pins are the collector of the reaches approximately 90% of its programmed voltage, internal NPN bipolar power transistor for switching regu- PGOOD will be pulled to ground. This will pull down on the lator 2. These pins must be tied together. Minimize trace gate of the MOSFET, connecting AV area at these pins to keep EMI down. DD. A 100k pull-up 1943fa 8
