Datasheet LT1767, LT1767-1.8, LT1767-2.5, LT1767-3.3, LT1767-5 (Analog Devices) - 8

LT1767/LT1767-1.8/ LT1767-2.5/LT1767-3.3/LT1767-5
applicaTions inForMaTion FB RESISTOR NETWORK
(~0.4V at maximum load). This leads to a minimum input If an output voltage of 1.8V, 2.5V, 3.3V or 5V is required, the voltage of: respective fixed option part, -1.8, -2.5, -3.3 or -5, should be VOUT + VD used. The FB pin is tied directly to the output; the necessary VIN(MIN) = – V DC D + VSW resistive divider is already included on the part. For other MAX voltage outputs, the adjustable part should be used and an with DCMAX = 0.80 at output current below 0.5A, and external resistor divider added. The suggested resistor (R2) DCMAX = 0.75 at higher loads. The maximum duty cycle from FB to ground is 10k. This reduces the contribution of decreases when the LT1767 is synchronized to an external FB input bias current to output voltage to less than 0.25%. clock; DCMAX = 1 – 0.25µs • fCLK. The formula for the resistor (R1) from VOUT to FB is: The maximum input voltage is determined by the absolute R2 (V ) maximum ratings of the V R1= OUT −1.2 IN and BOOST pins and by the 1.2−R2(0.25µA) minimum duty cycle DCMIN = 0.16: V V OUT + VD IN(MAX) = – VD + VSW DCMIN LT1767 VSW OUTPUT ERROR For a 12V input, the lowest practical output voltage is AMPLIFIER 1.8V. Minimum duty cycle will increase when the LT1767 + 1.2V is synchronized; DC gm R1 MIN = 0.11µs • fCLK. Note that this is FB + a restriction on the operating input voltage; the circuit – will tolerate transient inputs up to the absolute maximum R2 10k ratings of the VIN and BOOST pins, provided the output 1767 F02 is not shorted. VC GND For wider input voltage range, consult the related parts
Figure 2. Feedback Network
table on the last page of this data sheet.
INPUT VOLTAGE RANGE INPUT CAPACITOR
The input voltage range for LT1767 applications depends on the output voltage, the absolute maximum ratings of Step-down regulators draw current from the input supply in the VIN and BOOST pins, and the operating frequency. pulses. The rise and fall times of these pulses are very fast. The input capacitor is required to reduce the voltage ripple The minimum input voltage is determined by either the this causes at the input of LT1767 and force the switching LT1767’s minimum operating voltage of 2.73V or by its current into a tight local loop, thereby minimizing EMI. The maximum duty cycle. The duty cycle is the fraction of RMS ripple current can be calculated from: time that the internal switch is on and is determined by the input and output voltages: I 2 RIPPLE R ( MS) =IOUT VOUT (VIN − VOUT) / VIN VOUT + VD DC = VIN – VSW + VD Higher value, lower cost ceramic capacitors are now available in smaller case sizes. These are ideal for input bypassing where VD is the forward voltage drop of the catch diode since their high frequency capacitive nature removes most (~0.4V) and VSW is the voltage drop of the internal switch ripple current rating and turn-on surge problems. At higher switching frequency, the energy storage requirement of the 1767fb 8 For more information www.linear.com/LT1767 Document Outline Description Typical Application Absolute Maximum Ratings Electrical Characteristics Typical Application